forked from Minki/linux
8f32b90981
The cpdma has 8 rate limited tx channels. This patch adds ability for cpdma driver to use 8 tx h/w shapers. If at least one channel is not rate limited then it must have higher number, this is because the rate limited channels have to have higher priority then not rate limited channels. The channel priority is set in low-hi direction already, so that when a new channel is added with ethtool and it doesn't have rate yet, it cannot affect on rate limited channels. It can be useful for TSN streams and just in cases when h/w rate limited channels are needed. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
118 lines
3.7 KiB
C
118 lines
3.7 KiB
C
/*
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* Texas Instruments CPDMA Driver
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*
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* Copyright (C) 2010 Texas Instruments
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DAVINCI_CPDMA_H__
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#define __DAVINCI_CPDMA_H__
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#define CPDMA_MAX_CHANNELS BITS_PER_LONG
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#define CPDMA_RX_SOURCE_PORT(__status__) ((__status__ >> 16) & 0x7)
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#define CPDMA_EOI_RX_THRESH 0x0
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#define CPDMA_EOI_RX 0x1
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#define CPDMA_EOI_TX 0x2
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#define CPDMA_EOI_MISC 0x3
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struct cpdma_params {
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struct device *dev;
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void __iomem *dmaregs;
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void __iomem *txhdp, *rxhdp, *txcp, *rxcp;
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void __iomem *rxthresh, *rxfree;
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int num_chan;
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bool has_soft_reset;
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int min_packet_size;
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u32 desc_mem_phys;
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u32 desc_hw_addr;
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int desc_mem_size;
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int desc_align;
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u32 bus_freq_mhz;
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/*
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* Some instances of embedded cpdma controllers have extra control and
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* status registers. The following flag enables access to these
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* "extended" registers.
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*/
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bool has_ext_regs;
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};
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struct cpdma_chan_stats {
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u32 head_enqueue;
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u32 tail_enqueue;
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u32 pad_enqueue;
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u32 misqueued;
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u32 desc_alloc_fail;
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u32 pad_alloc_fail;
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u32 runt_receive_buff;
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u32 runt_transmit_buff;
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u32 empty_dequeue;
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u32 busy_dequeue;
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u32 good_dequeue;
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u32 requeue;
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u32 teardown_dequeue;
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};
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struct cpdma_ctlr;
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struct cpdma_chan;
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typedef void (*cpdma_handler_fn)(void *token, int len, int status);
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struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params);
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int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
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int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
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int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
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struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
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cpdma_handler_fn handler, int rx_type);
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int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan);
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int cpdma_chan_destroy(struct cpdma_chan *chan);
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int cpdma_chan_start(struct cpdma_chan *chan);
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int cpdma_chan_stop(struct cpdma_chan *chan);
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int cpdma_chan_get_stats(struct cpdma_chan *chan,
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struct cpdma_chan_stats *stats);
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int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
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int len, int directed);
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int cpdma_chan_process(struct cpdma_chan *chan, int quota);
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int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
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void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value);
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int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
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u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr);
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u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr);
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bool cpdma_check_free_tx_desc(struct cpdma_chan *chan);
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int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight);
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int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate);
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u32 cpdma_chan_get_rate(struct cpdma_chan *ch);
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u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr);
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enum cpdma_control {
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CPDMA_TX_RLIM, /* read-write */
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CPDMA_CMD_IDLE, /* write-only */
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CPDMA_COPY_ERROR_FRAMES, /* read-write */
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CPDMA_RX_OFF_LEN_UPDATE, /* read-write */
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CPDMA_RX_OWNERSHIP_FLIP, /* read-write */
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CPDMA_TX_PRIO_FIXED, /* read-write */
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CPDMA_STAT_IDLE, /* read-only */
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CPDMA_STAT_TX_ERR_CHAN, /* read-only */
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CPDMA_STAT_TX_ERR_CODE, /* read-only */
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CPDMA_STAT_RX_ERR_CHAN, /* read-only */
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CPDMA_STAT_RX_ERR_CODE, /* read-only */
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CPDMA_RX_BUFFER_OFFSET, /* read-write */
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};
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int cpdma_control_get(struct cpdma_ctlr *ctlr, int control);
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int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value);
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#endif
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