Swapnil Jakhade 8a1b82d744 phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration ... Add register sequences for PCIe + QSGMII PHY multilink configuration. PHY configuration for multi-link operation is done in two steps. e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes. Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this case, PLLLC is used for PCIe and PLLLC1 is used for QSGMII. PHY is configured in two steps as described below. [1] For first step, the register values are selected as [TYPE_PCIE][TYPE_QSGMII][ssc]. This will configure PHY registers associated for PCIe involving PLLLC registers and registers for first 2 lanes of PHY. [2] In second step, the register values are selected as [TYPE_QSGMII][TYPE_PCIE][ssc]. This will configure PHY registers associated for QSGMII involving PLLLC1 registers and registers for other 2 lanes of PHY. This completes the PHY configuration for multilink operation. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-14-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2021-12-27 16:35:09 +05:30
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cdns-dphy.c	phy: cadence: convert to devm_platform_ioremap_resource	2020-11-16 12:47:46 +05:30
Kconfig	phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)	2021-03-31 16:43:21 +05:30
Makefile	phy: cadence: salvo: add salvo phy driver	2020-05-07 09:46:36 +05:30
phy-cadence-salvo.c	phy: cadence: convert to devm_platform_ioremap_resource	2020-11-16 12:47:46 +05:30
phy-cadence-sierra.c	phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration	2021-12-27 16:35:09 +05:30
phy-cadence-torrent.c	phy: cadence-torrent: use swap() to make code cleaner	2021-11-23 11:24:30 +05:30