forked from Minki/linux
e16415313c
Currently, all imx pinctrl drivers maintain a big array of struct imx_pin_reg which hard-codes data like register offset and mux mode setting for each pin function. Every time a new imx SoC support is added, we need to add such a big mount of data. With moving to single kernel build, it's only matter of time to be blamed on memory consuming. With DTC pre-processor support in place, the patch moves all these data into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and changing the PIN_FUNC_ID parsing code a little bit. The pin id gets re-numbered based on mux register offset, or config register offset if the pin has no mux register, so that kernel can identify the pin id from register offsets provided by device tree. As a bonus point of the change, those arbitrary magic numbers standing for particular PIN_FUNC_ID in device tree sources are now replaced by macros to improve the readability of dts files. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
173 lines
3.7 KiB
Plaintext
173 lines
3.7 KiB
Plaintext
/*
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* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "imx53.dtsi"
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/ {
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model = "TQ TQMa53";
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compatible = "tq,tqma53", "fsl,imx53";
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memory {
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reg = <0x70000000 0x40000000>; /* Up to 1GiB */
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};
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regulators {
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compatible = "simple-bus";
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reg_3p3v: 3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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&esdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc2_1>;
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wp-gpios = <&gpio1 2 0>;
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cd-gpios = <&gpio1 4 0>;
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status = "disabled";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3_2>;
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status = "disabled";
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1_1>;
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fsl,spi-num-chipselects = <4>;
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cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
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<&gpio3 24 0>, <&gpio3 25 0>;
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status = "disabled";
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};
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&esdhc3 { /* EMMC */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc3_1>;
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vmmc-supply = <®_3p3v>;
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non-removable;
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bus-width = <8>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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i2s {
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pinctrl_i2s_1: i2s-grp1 {
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fsl,pins = <
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MX53_PAD_GPIO_19__GPIO4_5 0x10000 /* I2S_MCLK */
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MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x10000 /* I2S_SCLK */
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MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x10000 /* I2S_DOUT */
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MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x10000 /* I2S_LRCLK */
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MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x10000 /* I2S_DIN */
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>;
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};
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};
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hog {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x10000 /* VSYNC */
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MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x10000 /* HSYNC */
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MX53_PAD_PATA_DA_1__GPIO7_7 0x10000 /* LCD_BLT_EN */
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MX53_PAD_PATA_DA_2__GPIO7_8 0x10000 /* LCD_RESET */
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MX53_PAD_PATA_DATA5__GPIO2_5 0x10000 /* LCD_POWER */
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MX53_PAD_PATA_DATA6__GPIO2_6 0x10000 /* PMIC_INT */
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MX53_PAD_PATA_DATA14__GPIO2_14 0x10000 /* CSI_RST */
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MX53_PAD_PATA_DATA15__GPIO2_15 0x10000 /* CSI_PWDN */
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MX53_PAD_GPIO_0__GPIO1_0 0x10000 /* SYSTEM_DOWN */
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MX53_PAD_GPIO_3__GPIO1_3 0x10000
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>;
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};
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_2>;
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fsl,uart-has-rtscts;
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status = "disabled";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2_1>;
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status = "disabled";
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1_2>;
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status = "disabled";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can2_1>;
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status = "disabled";
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3_1>;
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status = "disabled";
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};
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&cspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_cspi_1>;
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fsl,spi-num-chipselects = <3>;
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cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
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<&gpio1 21 0>;
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status = "disabled";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2_1>;
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status = "okay";
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pmic: mc34708@8 {
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compatible = "fsl,mc34708";
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reg = <0x8>;
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fsl,mc13xxx-uses-rtc;
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interrupt-parent = <&gpio2>;
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interrupts = <6 8>; /* PDATA_DATA6, low active */
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};
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sensor1: lm75@48 {
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compatible = "lm75";
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reg = <0x48>;
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};
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eeprom: 24c64@50 {
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compatible = "at,24c64";
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pagesize = <32>;
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reg = <0x50>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec_1>;
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phy-mode = "rmii";
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status = "disabled";
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};
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