forked from Minki/linux
5e79cb29dd
Some Layerscape SoCs use a simple MSI controller implementation. It contains only two SCFG register to trigger and describe a group 32 MSI interrupts. The patch adds bindings to describe the controller. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
31 lines
1.0 KiB
Plaintext
31 lines
1.0 KiB
Plaintext
* Freescale Layerscape SCFG PCIe MSI controller
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Required properties:
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- compatible: should be "fsl,<soc-name>-msi" to identify
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Layerscape PCIe MSI controller block such as:
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"fsl,1s1021a-msi"
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"fsl,1s1043a-msi"
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- msi-controller: indicates that this is a PCIe MSI controller node
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- reg: physical base address of the controller and length of memory mapped.
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- interrupts: an interrupt to the parent interrupt controller.
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Optional properties:
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- interrupt-parent: the phandle to the parent interrupt controller.
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This interrupt controller hardware is a second level interrupt controller that
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is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
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platforms. If interrupt-parent is not provided, the default parent interrupt
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controller will be used.
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Each PCIe node needs to have property msi-parent that points to
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MSI controller node
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Examples:
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msi1: msi-controller@1571000 {
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compatible = "fsl,1s1043a-msi";
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reg = <0x0 0x1571000 0x0 0x8>,
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msi-controller;
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interrupts = <0 116 0x4>;
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};
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