forked from Minki/linux
4642019dc4
The GIC Hypervisor Configuration Register is used to enable the delivery of virtual interupts to a guest, as well as to define in which conditions maintenance interrupts are delivered to the host. This register doesn't contain any information that we need to read back (the EOIcount is utterly useless for us). So let's save ourselves some cycles, and not save it before writing zero to it. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
647 lines
16 KiB
ArmAsm
647 lines
16 KiB
ArmAsm
#include <linux/irqchip/arm-gic.h>
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#include <asm/assembler.h>
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#define VCPU_USR_REG(_reg_nr) (VCPU_USR_REGS + (_reg_nr * 4))
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#define VCPU_USR_SP (VCPU_USR_REG(13))
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#define VCPU_USR_LR (VCPU_USR_REG(14))
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#define CP15_OFFSET(_cp15_reg_idx) (VCPU_CP15 + (_cp15_reg_idx * 4))
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/*
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* Many of these macros need to access the VCPU structure, which is always
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* held in r0. These macros should never clobber r1, as it is used to hold the
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* exception code on the return path (except of course the macro that switches
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* all the registers before the final jump to the VM).
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*/
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vcpu .req r0 @ vcpu pointer always in r0
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/* Clobbers {r2-r6} */
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.macro store_vfp_state vfp_base
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@ The VFPFMRX and VFPFMXR macros are the VMRS and VMSR instructions
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VFPFMRX r2, FPEXC
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@ Make sure VFP is enabled so we can touch the registers.
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orr r6, r2, #FPEXC_EN
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VFPFMXR FPEXC, r6
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VFPFMRX r3, FPSCR
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tst r2, #FPEXC_EX @ Check for VFP Subarchitecture
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beq 1f
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@ If FPEXC_EX is 0, then FPINST/FPINST2 reads are upredictable, so
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@ we only need to save them if FPEXC_EX is set.
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VFPFMRX r4, FPINST
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tst r2, #FPEXC_FP2V
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VFPFMRX r5, FPINST2, ne @ vmrsne
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bic r6, r2, #FPEXC_EX @ FPEXC_EX disable
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VFPFMXR FPEXC, r6
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1:
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VFPFSTMIA \vfp_base, r6 @ Save VFP registers
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stm \vfp_base, {r2-r5} @ Save FPEXC, FPSCR, FPINST, FPINST2
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.endm
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/* Assume FPEXC_EN is on and FPEXC_EX is off, clobbers {r2-r6} */
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.macro restore_vfp_state vfp_base
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VFPFLDMIA \vfp_base, r6 @ Load VFP registers
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ldm \vfp_base, {r2-r5} @ Load FPEXC, FPSCR, FPINST, FPINST2
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VFPFMXR FPSCR, r3
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tst r2, #FPEXC_EX @ Check for VFP Subarchitecture
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beq 1f
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VFPFMXR FPINST, r4
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tst r2, #FPEXC_FP2V
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VFPFMXR FPINST2, r5, ne
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1:
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VFPFMXR FPEXC, r2 @ FPEXC (last, in case !EN)
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.endm
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/* These are simply for the macros to work - value don't have meaning */
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.equ usr, 0
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.equ svc, 1
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.equ abt, 2
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.equ und, 3
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.equ irq, 4
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.equ fiq, 5
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.macro push_host_regs_mode mode
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mrs r2, SP_\mode
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mrs r3, LR_\mode
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mrs r4, SPSR_\mode
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push {r2, r3, r4}
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.endm
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/*
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* Store all host persistent registers on the stack.
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* Clobbers all registers, in all modes, except r0 and r1.
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*/
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.macro save_host_regs
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/* Hyp regs. Only ELR_hyp (SPSR_hyp already saved) */
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mrs r2, ELR_hyp
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push {r2}
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/* usr regs */
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push {r4-r12} @ r0-r3 are always clobbered
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mrs r2, SP_usr
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mov r3, lr
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push {r2, r3}
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push_host_regs_mode svc
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push_host_regs_mode abt
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push_host_regs_mode und
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push_host_regs_mode irq
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/* fiq regs */
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mrs r2, r8_fiq
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mrs r3, r9_fiq
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mrs r4, r10_fiq
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mrs r5, r11_fiq
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mrs r6, r12_fiq
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mrs r7, SP_fiq
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mrs r8, LR_fiq
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mrs r9, SPSR_fiq
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push {r2-r9}
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.endm
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.macro pop_host_regs_mode mode
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pop {r2, r3, r4}
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msr SP_\mode, r2
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msr LR_\mode, r3
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msr SPSR_\mode, r4
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.endm
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/*
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* Restore all host registers from the stack.
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* Clobbers all registers, in all modes, except r0 and r1.
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*/
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.macro restore_host_regs
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pop {r2-r9}
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msr r8_fiq, r2
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msr r9_fiq, r3
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msr r10_fiq, r4
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msr r11_fiq, r5
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msr r12_fiq, r6
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msr SP_fiq, r7
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msr LR_fiq, r8
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msr SPSR_fiq, r9
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pop_host_regs_mode irq
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pop_host_regs_mode und
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pop_host_regs_mode abt
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pop_host_regs_mode svc
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pop {r2, r3}
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msr SP_usr, r2
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mov lr, r3
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pop {r4-r12}
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pop {r2}
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msr ELR_hyp, r2
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.endm
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/*
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* Restore SP, LR and SPSR for a given mode. offset is the offset of
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* this mode's registers from the VCPU base.
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*
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* Assumes vcpu pointer in vcpu reg
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*
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* Clobbers r1, r2, r3, r4.
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*/
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.macro restore_guest_regs_mode mode, offset
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add r1, vcpu, \offset
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ldm r1, {r2, r3, r4}
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msr SP_\mode, r2
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msr LR_\mode, r3
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msr SPSR_\mode, r4
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.endm
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/*
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* Restore all guest registers from the vcpu struct.
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*
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* Assumes vcpu pointer in vcpu reg
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*
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* Clobbers *all* registers.
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*/
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.macro restore_guest_regs
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restore_guest_regs_mode svc, #VCPU_SVC_REGS
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restore_guest_regs_mode abt, #VCPU_ABT_REGS
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restore_guest_regs_mode und, #VCPU_UND_REGS
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restore_guest_regs_mode irq, #VCPU_IRQ_REGS
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add r1, vcpu, #VCPU_FIQ_REGS
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ldm r1, {r2-r9}
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msr r8_fiq, r2
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msr r9_fiq, r3
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msr r10_fiq, r4
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msr r11_fiq, r5
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msr r12_fiq, r6
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msr SP_fiq, r7
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msr LR_fiq, r8
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msr SPSR_fiq, r9
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@ Load return state
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ldr r2, [vcpu, #VCPU_PC]
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ldr r3, [vcpu, #VCPU_CPSR]
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msr ELR_hyp, r2
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msr SPSR_cxsf, r3
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@ Load user registers
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ldr r2, [vcpu, #VCPU_USR_SP]
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ldr r3, [vcpu, #VCPU_USR_LR]
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msr SP_usr, r2
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mov lr, r3
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add vcpu, vcpu, #(VCPU_USR_REGS)
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ldm vcpu, {r0-r12}
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.endm
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/*
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* Save SP, LR and SPSR for a given mode. offset is the offset of
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* this mode's registers from the VCPU base.
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*
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* Assumes vcpu pointer in vcpu reg
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*
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* Clobbers r2, r3, r4, r5.
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*/
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.macro save_guest_regs_mode mode, offset
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add r2, vcpu, \offset
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mrs r3, SP_\mode
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mrs r4, LR_\mode
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mrs r5, SPSR_\mode
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stm r2, {r3, r4, r5}
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.endm
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/*
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* Save all guest registers to the vcpu struct
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* Expects guest's r0, r1, r2 on the stack.
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*
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* Assumes vcpu pointer in vcpu reg
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*
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* Clobbers r2, r3, r4, r5.
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*/
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.macro save_guest_regs
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@ Store usr registers
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add r2, vcpu, #VCPU_USR_REG(3)
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stm r2, {r3-r12}
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add r2, vcpu, #VCPU_USR_REG(0)
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pop {r3, r4, r5} @ r0, r1, r2
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stm r2, {r3, r4, r5}
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mrs r2, SP_usr
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mov r3, lr
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str r2, [vcpu, #VCPU_USR_SP]
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str r3, [vcpu, #VCPU_USR_LR]
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@ Store return state
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mrs r2, ELR_hyp
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mrs r3, spsr
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str r2, [vcpu, #VCPU_PC]
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str r3, [vcpu, #VCPU_CPSR]
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@ Store other guest registers
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save_guest_regs_mode svc, #VCPU_SVC_REGS
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save_guest_regs_mode abt, #VCPU_ABT_REGS
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save_guest_regs_mode und, #VCPU_UND_REGS
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save_guest_regs_mode irq, #VCPU_IRQ_REGS
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.endm
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/* Reads cp15 registers from hardware and stores them in memory
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* @store_to_vcpu: If 0, registers are written in-order to the stack,
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* otherwise to the VCPU struct pointed to by vcpup
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*
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* Assumes vcpu pointer in vcpu reg
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*
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* Clobbers r2 - r12
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*/
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.macro read_cp15_state store_to_vcpu
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mrc p15, 0, r2, c1, c0, 0 @ SCTLR
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mrc p15, 0, r3, c1, c0, 2 @ CPACR
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mrc p15, 0, r4, c2, c0, 2 @ TTBCR
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mrc p15, 0, r5, c3, c0, 0 @ DACR
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mrrc p15, 0, r6, r7, c2 @ TTBR 0
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mrrc p15, 1, r8, r9, c2 @ TTBR 1
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mrc p15, 0, r10, c10, c2, 0 @ PRRR
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mrc p15, 0, r11, c10, c2, 1 @ NMRR
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mrc p15, 2, r12, c0, c0, 0 @ CSSELR
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.if \store_to_vcpu == 0
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push {r2-r12} @ Push CP15 registers
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.else
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str r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
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str r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
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str r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
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str r5, [vcpu, #CP15_OFFSET(c3_DACR)]
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add r2, vcpu, #CP15_OFFSET(c2_TTBR0)
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strd r6, r7, [r2]
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add r2, vcpu, #CP15_OFFSET(c2_TTBR1)
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strd r8, r9, [r2]
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str r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
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str r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
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str r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
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.endif
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mrc p15, 0, r2, c13, c0, 1 @ CID
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mrc p15, 0, r3, c13, c0, 2 @ TID_URW
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mrc p15, 0, r4, c13, c0, 3 @ TID_URO
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mrc p15, 0, r5, c13, c0, 4 @ TID_PRIV
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mrc p15, 0, r6, c5, c0, 0 @ DFSR
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mrc p15, 0, r7, c5, c0, 1 @ IFSR
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mrc p15, 0, r8, c5, c1, 0 @ ADFSR
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mrc p15, 0, r9, c5, c1, 1 @ AIFSR
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mrc p15, 0, r10, c6, c0, 0 @ DFAR
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mrc p15, 0, r11, c6, c0, 2 @ IFAR
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mrc p15, 0, r12, c12, c0, 0 @ VBAR
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.if \store_to_vcpu == 0
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push {r2-r12} @ Push CP15 registers
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.else
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str r2, [vcpu, #CP15_OFFSET(c13_CID)]
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str r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
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str r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
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str r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
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str r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
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str r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
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str r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
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str r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
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str r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
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str r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
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str r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
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.endif
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mrc p15, 0, r2, c14, c1, 0 @ CNTKCTL
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mrrc p15, 0, r4, r5, c7 @ PAR
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mrc p15, 0, r6, c10, c3, 0 @ AMAIR0
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mrc p15, 0, r7, c10, c3, 1 @ AMAIR1
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.if \store_to_vcpu == 0
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push {r2,r4-r7}
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.else
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str r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
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add r12, vcpu, #CP15_OFFSET(c7_PAR)
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strd r4, r5, [r12]
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str r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)]
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str r7, [vcpu, #CP15_OFFSET(c10_AMAIR1)]
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.endif
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.endm
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/*
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* Reads cp15 registers from memory and writes them to hardware
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* @read_from_vcpu: If 0, registers are read in-order from the stack,
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* otherwise from the VCPU struct pointed to by vcpup
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*
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* Assumes vcpu pointer in vcpu reg
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*/
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.macro write_cp15_state read_from_vcpu
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.if \read_from_vcpu == 0
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pop {r2,r4-r7}
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.else
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ldr r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
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add r12, vcpu, #CP15_OFFSET(c7_PAR)
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ldrd r4, r5, [r12]
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ldr r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)]
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ldr r7, [vcpu, #CP15_OFFSET(c10_AMAIR1)]
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.endif
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mcr p15, 0, r2, c14, c1, 0 @ CNTKCTL
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mcrr p15, 0, r4, r5, c7 @ PAR
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mcr p15, 0, r6, c10, c3, 0 @ AMAIR0
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mcr p15, 0, r7, c10, c3, 1 @ AMAIR1
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.if \read_from_vcpu == 0
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pop {r2-r12}
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.else
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ldr r2, [vcpu, #CP15_OFFSET(c13_CID)]
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ldr r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
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ldr r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
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ldr r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
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ldr r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
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ldr r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
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ldr r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
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ldr r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
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ldr r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
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ldr r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
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ldr r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
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.endif
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mcr p15, 0, r2, c13, c0, 1 @ CID
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mcr p15, 0, r3, c13, c0, 2 @ TID_URW
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mcr p15, 0, r4, c13, c0, 3 @ TID_URO
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mcr p15, 0, r5, c13, c0, 4 @ TID_PRIV
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mcr p15, 0, r6, c5, c0, 0 @ DFSR
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mcr p15, 0, r7, c5, c0, 1 @ IFSR
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mcr p15, 0, r8, c5, c1, 0 @ ADFSR
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mcr p15, 0, r9, c5, c1, 1 @ AIFSR
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mcr p15, 0, r10, c6, c0, 0 @ DFAR
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mcr p15, 0, r11, c6, c0, 2 @ IFAR
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mcr p15, 0, r12, c12, c0, 0 @ VBAR
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.if \read_from_vcpu == 0
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pop {r2-r12}
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.else
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ldr r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
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ldr r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
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ldr r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
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ldr r5, [vcpu, #CP15_OFFSET(c3_DACR)]
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add r12, vcpu, #CP15_OFFSET(c2_TTBR0)
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ldrd r6, r7, [r12]
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add r12, vcpu, #CP15_OFFSET(c2_TTBR1)
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ldrd r8, r9, [r12]
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ldr r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
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ldr r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
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ldr r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
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.endif
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mcr p15, 0, r2, c1, c0, 0 @ SCTLR
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mcr p15, 0, r3, c1, c0, 2 @ CPACR
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mcr p15, 0, r4, c2, c0, 2 @ TTBCR
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mcr p15, 0, r5, c3, c0, 0 @ DACR
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mcrr p15, 0, r6, r7, c2 @ TTBR 0
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mcrr p15, 1, r8, r9, c2 @ TTBR 1
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mcr p15, 0, r10, c10, c2, 0 @ PRRR
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mcr p15, 0, r11, c10, c2, 1 @ NMRR
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mcr p15, 2, r12, c0, c0, 0 @ CSSELR
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.endm
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/*
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* Save the VGIC CPU state into memory
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*
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* Assumes vcpu pointer in vcpu reg
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*/
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.macro save_vgic_state
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/* Get VGIC VCTRL base into r2 */
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ldr r2, [vcpu, #VCPU_KVM]
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ldr r2, [r2, #KVM_VGIC_VCTRL]
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cmp r2, #0
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beq 2f
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/* Compute the address of struct vgic_cpu */
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add r11, vcpu, #VCPU_VGIC_CPU
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/* Save all interesting registers */
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ldr r4, [r2, #GICH_VMCR]
|
|
ldr r5, [r2, #GICH_MISR]
|
|
ldr r6, [r2, #GICH_EISR0]
|
|
ldr r7, [r2, #GICH_EISR1]
|
|
ldr r8, [r2, #GICH_ELRSR0]
|
|
ldr r9, [r2, #GICH_ELRSR1]
|
|
ldr r10, [r2, #GICH_APR]
|
|
ARM_BE8(rev r4, r4 )
|
|
ARM_BE8(rev r5, r5 )
|
|
ARM_BE8(rev r6, r6 )
|
|
ARM_BE8(rev r7, r7 )
|
|
ARM_BE8(rev r8, r8 )
|
|
ARM_BE8(rev r9, r9 )
|
|
ARM_BE8(rev r10, r10 )
|
|
|
|
str r4, [r11, #VGIC_V2_CPU_VMCR]
|
|
str r5, [r11, #VGIC_V2_CPU_MISR]
|
|
#ifdef CONFIG_CPU_ENDIAN_BE8
|
|
str r6, [r11, #(VGIC_V2_CPU_EISR + 4)]
|
|
str r7, [r11, #VGIC_V2_CPU_EISR]
|
|
str r8, [r11, #(VGIC_V2_CPU_ELRSR + 4)]
|
|
str r9, [r11, #VGIC_V2_CPU_ELRSR]
|
|
#else
|
|
str r6, [r11, #VGIC_V2_CPU_EISR]
|
|
str r7, [r11, #(VGIC_V2_CPU_EISR + 4)]
|
|
str r8, [r11, #VGIC_V2_CPU_ELRSR]
|
|
str r9, [r11, #(VGIC_V2_CPU_ELRSR + 4)]
|
|
#endif
|
|
str r10, [r11, #VGIC_V2_CPU_APR]
|
|
|
|
/* Clear GICH_HCR */
|
|
mov r5, #0
|
|
str r5, [r2, #GICH_HCR]
|
|
|
|
/* Save list registers */
|
|
add r2, r2, #GICH_LR0
|
|
add r3, r11, #VGIC_V2_CPU_LR
|
|
ldr r4, [r11, #VGIC_CPU_NR_LR]
|
|
1: ldr r6, [r2], #4
|
|
ARM_BE8(rev r6, r6 )
|
|
str r6, [r3], #4
|
|
subs r4, r4, #1
|
|
bne 1b
|
|
2:
|
|
.endm
|
|
|
|
/*
|
|
* Restore the VGIC CPU state from memory
|
|
*
|
|
* Assumes vcpu pointer in vcpu reg
|
|
*/
|
|
.macro restore_vgic_state
|
|
/* Get VGIC VCTRL base into r2 */
|
|
ldr r2, [vcpu, #VCPU_KVM]
|
|
ldr r2, [r2, #KVM_VGIC_VCTRL]
|
|
cmp r2, #0
|
|
beq 2f
|
|
|
|
/* Compute the address of struct vgic_cpu */
|
|
add r11, vcpu, #VCPU_VGIC_CPU
|
|
|
|
/* We only restore a minimal set of registers */
|
|
ldr r3, [r11, #VGIC_V2_CPU_HCR]
|
|
ldr r4, [r11, #VGIC_V2_CPU_VMCR]
|
|
ldr r8, [r11, #VGIC_V2_CPU_APR]
|
|
ARM_BE8(rev r3, r3 )
|
|
ARM_BE8(rev r4, r4 )
|
|
ARM_BE8(rev r8, r8 )
|
|
|
|
str r3, [r2, #GICH_HCR]
|
|
str r4, [r2, #GICH_VMCR]
|
|
str r8, [r2, #GICH_APR]
|
|
|
|
/* Restore list registers */
|
|
add r2, r2, #GICH_LR0
|
|
add r3, r11, #VGIC_V2_CPU_LR
|
|
ldr r4, [r11, #VGIC_CPU_NR_LR]
|
|
1: ldr r6, [r3], #4
|
|
ARM_BE8(rev r6, r6 )
|
|
str r6, [r2], #4
|
|
subs r4, r4, #1
|
|
bne 1b
|
|
2:
|
|
.endm
|
|
|
|
#define CNTHCTL_PL1PCTEN (1 << 0)
|
|
#define CNTHCTL_PL1PCEN (1 << 1)
|
|
|
|
/*
|
|
* Save the timer state onto the VCPU and allow physical timer/counter access
|
|
* for the host.
|
|
*
|
|
* Assumes vcpu pointer in vcpu reg
|
|
* Clobbers r2-r5
|
|
*/
|
|
.macro save_timer_state
|
|
ldr r4, [vcpu, #VCPU_KVM]
|
|
ldr r2, [r4, #KVM_TIMER_ENABLED]
|
|
cmp r2, #0
|
|
beq 1f
|
|
|
|
mrc p15, 0, r2, c14, c3, 1 @ CNTV_CTL
|
|
str r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
|
|
bic r2, #1 @ Clear ENABLE
|
|
mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL
|
|
isb
|
|
|
|
mrrc p15, 3, rr_lo_hi(r2, r3), c14 @ CNTV_CVAL
|
|
ldr r4, =VCPU_TIMER_CNTV_CVAL
|
|
add r5, vcpu, r4
|
|
strd r2, r3, [r5]
|
|
|
|
@ Ensure host CNTVCT == CNTPCT
|
|
mov r2, #0
|
|
mcrr p15, 4, r2, r2, c14 @ CNTVOFF
|
|
|
|
1:
|
|
@ Allow physical timer/counter access for the host
|
|
mrc p15, 4, r2, c14, c1, 0 @ CNTHCTL
|
|
orr r2, r2, #(CNTHCTL_PL1PCEN | CNTHCTL_PL1PCTEN)
|
|
mcr p15, 4, r2, c14, c1, 0 @ CNTHCTL
|
|
.endm
|
|
|
|
/*
|
|
* Load the timer state from the VCPU and deny physical timer/counter access
|
|
* for the host.
|
|
*
|
|
* Assumes vcpu pointer in vcpu reg
|
|
* Clobbers r2-r5
|
|
*/
|
|
.macro restore_timer_state
|
|
@ Disallow physical timer access for the guest
|
|
@ Physical counter access is allowed
|
|
mrc p15, 4, r2, c14, c1, 0 @ CNTHCTL
|
|
orr r2, r2, #CNTHCTL_PL1PCTEN
|
|
bic r2, r2, #CNTHCTL_PL1PCEN
|
|
mcr p15, 4, r2, c14, c1, 0 @ CNTHCTL
|
|
|
|
ldr r4, [vcpu, #VCPU_KVM]
|
|
ldr r2, [r4, #KVM_TIMER_ENABLED]
|
|
cmp r2, #0
|
|
beq 1f
|
|
|
|
ldr r2, [r4, #KVM_TIMER_CNTVOFF]
|
|
ldr r3, [r4, #(KVM_TIMER_CNTVOFF + 4)]
|
|
mcrr p15, 4, rr_lo_hi(r2, r3), c14 @ CNTVOFF
|
|
|
|
ldr r4, =VCPU_TIMER_CNTV_CVAL
|
|
add r5, vcpu, r4
|
|
ldrd r2, r3, [r5]
|
|
mcrr p15, 3, rr_lo_hi(r2, r3), c14 @ CNTV_CVAL
|
|
isb
|
|
|
|
ldr r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
|
|
and r2, r2, #3
|
|
mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL
|
|
1:
|
|
.endm
|
|
|
|
.equ vmentry, 0
|
|
.equ vmexit, 1
|
|
|
|
/* Configures the HSTR (Hyp System Trap Register) on entry/return
|
|
* (hardware reset value is 0) */
|
|
.macro set_hstr operation
|
|
mrc p15, 4, r2, c1, c1, 3
|
|
ldr r3, =HSTR_T(15)
|
|
.if \operation == vmentry
|
|
orr r2, r2, r3 @ Trap CR{15}
|
|
.else
|
|
bic r2, r2, r3 @ Don't trap any CRx accesses
|
|
.endif
|
|
mcr p15, 4, r2, c1, c1, 3
|
|
.endm
|
|
|
|
/* Configures the HCPTR (Hyp Coprocessor Trap Register) on entry/return
|
|
* (hardware reset value is 0). Keep previous value in r2.
|
|
* An ISB is emited on vmexit/vmtrap, but executed on vmexit only if
|
|
* VFP wasn't already enabled (always executed on vmtrap).
|
|
* If a label is specified with vmexit, it is branched to if VFP wasn't
|
|
* enabled.
|
|
*/
|
|
.macro set_hcptr operation, mask, label = none
|
|
mrc p15, 4, r2, c1, c1, 2
|
|
ldr r3, =\mask
|
|
.if \operation == vmentry
|
|
orr r3, r2, r3 @ Trap coproc-accesses defined in mask
|
|
.else
|
|
bic r3, r2, r3 @ Don't trap defined coproc-accesses
|
|
.endif
|
|
mcr p15, 4, r3, c1, c1, 2
|
|
.if \operation != vmentry
|
|
.if \operation == vmexit
|
|
tst r2, #(HCPTR_TCP(10) | HCPTR_TCP(11))
|
|
beq 1f
|
|
.endif
|
|
isb
|
|
.if \label != none
|
|
b \label
|
|
.endif
|
|
1:
|
|
.endif
|
|
.endm
|
|
|
|
/* Configures the HDCR (Hyp Debug Configuration Register) on entry/return
|
|
* (hardware reset value is 0) */
|
|
.macro set_hdcr operation
|
|
mrc p15, 4, r2, c1, c1, 1
|
|
ldr r3, =(HDCR_TPM|HDCR_TPMCR)
|
|
.if \operation == vmentry
|
|
orr r2, r2, r3 @ Trap some perfmon accesses
|
|
.else
|
|
bic r2, r2, r3 @ Don't trap any perfmon accesses
|
|
.endif
|
|
mcr p15, 4, r2, c1, c1, 1
|
|
.endm
|
|
|
|
/* Enable/Disable: stage-2 trans., trap interrupts, trap wfi, trap smc */
|
|
.macro configure_hyp_role operation
|
|
.if \operation == vmentry
|
|
ldr r2, [vcpu, #VCPU_HCR]
|
|
ldr r3, [vcpu, #VCPU_IRQ_LINES]
|
|
orr r2, r2, r3
|
|
.else
|
|
mov r2, #0
|
|
.endif
|
|
mcr p15, 4, r2, c1, c1, 0 @ HCR
|
|
.endm
|
|
|
|
.macro load_vcpu
|
|
mrc p15, 4, vcpu, c13, c0, 2 @ HTPIDR
|
|
.endm
|