forked from Minki/linux
88e4ac68ea
According to the public datasheet all register bits in HHI_MPLL_CNTL7,
HHI_MPLL_CNTL8 and HHI_MPLL_CNTL9 default to zero. On all GX SoCs these
seem to be initialized by the bootloader to some default value.
However, on my Meson8 board they are not initialized, leading to a
division by zero in rate_from_params as the math is:
(parent_rate * SDM_DEN) / ((SDM_DEN * 0) + 0)
According to the datasheet, the minimum n2 value is 4. The rate provided
by the clock when n2 is less than this minimum is unpredictable. In such
case, we report an error.
Although the rate_from_params function was only introduced recently the
original bug has been there for much longer. It was only exposed
recently when the MPLL clocks were added to the Meson8b clock driver.
Fixes: 1c50da4f27 ("clk: meson: add mpll support")
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
241 lines
6.5 KiB
C
241 lines
6.5 KiB
C
/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (c) 2016 AmLogic, Inc.
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* Author: Michael Turquette <mturquette@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING
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*
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* BSD LICENSE
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*
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* Copyright (c) 2016 AmLogic, Inc.
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* Author: Michael Turquette <mturquette@baylibre.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* MultiPhase Locked Loops are outputs from a PLL with additional frequency
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* scaling capabilities. MPLL rates are calculated as:
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*
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* f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
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*/
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#include <linux/clk-provider.h>
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#include "clkc.h"
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#define SDM_DEN 16384
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#define N2_MIN 4
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#define N2_MAX 511
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#define to_meson_clk_mpll(_hw) container_of(_hw, struct meson_clk_mpll, hw)
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static long rate_from_params(unsigned long parent_rate,
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unsigned long sdm,
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unsigned long n2)
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{
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unsigned long divisor = (SDM_DEN * n2) + sdm;
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if (n2 < N2_MIN)
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return -EINVAL;
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return (parent_rate * SDM_DEN) / divisor;
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}
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static void params_from_rate(unsigned long requested_rate,
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unsigned long parent_rate,
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unsigned long *sdm,
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unsigned long *n2)
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{
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uint64_t div = parent_rate;
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unsigned long rem = do_div(div, requested_rate);
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if (div < N2_MIN) {
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*n2 = N2_MIN;
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*sdm = 0;
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} else if (div > N2_MAX) {
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*n2 = N2_MAX;
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*sdm = SDM_DEN - 1;
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} else {
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*n2 = div;
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*sdm = DIV_ROUND_UP(rem * SDM_DEN, requested_rate);
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}
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}
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static unsigned long mpll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
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struct parm *p;
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unsigned long reg, sdm, n2;
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long rate;
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p = &mpll->sdm;
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reg = readl(mpll->base + p->reg_off);
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sdm = PARM_GET(p->width, p->shift, reg);
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p = &mpll->n2;
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reg = readl(mpll->base + p->reg_off);
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n2 = PARM_GET(p->width, p->shift, reg);
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rate = rate_from_params(parent_rate, sdm, n2);
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if (rate < 0)
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return 0;
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return rate;
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}
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static long mpll_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned long sdm, n2;
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params_from_rate(rate, *parent_rate, &sdm, &n2);
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return rate_from_params(*parent_rate, sdm, n2);
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}
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static int mpll_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
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struct parm *p;
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unsigned long reg, sdm, n2;
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unsigned long flags = 0;
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params_from_rate(rate, parent_rate, &sdm, &n2);
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if (mpll->lock)
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spin_lock_irqsave(mpll->lock, flags);
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else
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__acquire(mpll->lock);
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p = &mpll->sdm;
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reg = readl(mpll->base + p->reg_off);
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reg = PARM_SET(p->width, p->shift, reg, sdm);
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writel(reg, mpll->base + p->reg_off);
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p = &mpll->sdm_en;
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reg = readl(mpll->base + p->reg_off);
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reg = PARM_SET(p->width, p->shift, reg, 1);
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writel(reg, mpll->base + p->reg_off);
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p = &mpll->n2;
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reg = readl(mpll->base + p->reg_off);
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reg = PARM_SET(p->width, p->shift, reg, n2);
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writel(reg, mpll->base + p->reg_off);
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if (mpll->lock)
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spin_unlock_irqrestore(mpll->lock, flags);
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else
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__release(mpll->lock);
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return 0;
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}
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static void mpll_enable_core(struct clk_hw *hw, int enable)
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{
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struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
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struct parm *p;
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unsigned long reg;
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unsigned long flags = 0;
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if (mpll->lock)
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spin_lock_irqsave(mpll->lock, flags);
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else
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__acquire(mpll->lock);
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p = &mpll->en;
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reg = readl(mpll->base + p->reg_off);
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reg = PARM_SET(p->width, p->shift, reg, enable ? 1 : 0);
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writel(reg, mpll->base + p->reg_off);
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if (mpll->lock)
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spin_unlock_irqrestore(mpll->lock, flags);
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else
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__release(mpll->lock);
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}
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static int mpll_enable(struct clk_hw *hw)
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{
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mpll_enable_core(hw, 1);
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return 0;
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}
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static void mpll_disable(struct clk_hw *hw)
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{
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mpll_enable_core(hw, 0);
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}
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static int mpll_is_enabled(struct clk_hw *hw)
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{
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struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
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struct parm *p;
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unsigned long reg;
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int en;
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p = &mpll->en;
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reg = readl(mpll->base + p->reg_off);
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en = PARM_GET(p->width, p->shift, reg);
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return en;
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}
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const struct clk_ops meson_clk_mpll_ro_ops = {
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.recalc_rate = mpll_recalc_rate,
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.round_rate = mpll_round_rate,
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.is_enabled = mpll_is_enabled,
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};
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const struct clk_ops meson_clk_mpll_ops = {
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.recalc_rate = mpll_recalc_rate,
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.round_rate = mpll_round_rate,
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.set_rate = mpll_set_rate,
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.enable = mpll_enable,
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.disable = mpll_disable,
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.is_enabled = mpll_is_enabled,
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};
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