Jian Xin 99c6fc6d7e clk: socfpga: clk-pll: Remove unused variable 'rc' ... Fix the following build warning: drivers/clk/socfpga/clk-pll.c: In function ‘__socfpga_pll_init’: drivers/clk/socfpga/clk-pll.c:83:6: warning: variable ‘rc’ set but not used [-Wunused-but-set-variable] Signed-off-by: Jian Xin <xinjian@yulong.com> Link: https://lore.kernel.org/r/20210609073742.722911-1-xinjian34324@163.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2021-06-27 17:33:21 -07:00
..
clk-agilex.c	clk: agilex/stratix10: add support for the 2nd bypass	2021-06-27 16:39:59 -07:00
clk-gate-a10.c	clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return	2021-04-07 16:29:31 -07:00
clk-gate-s10.c	clk: agilex/stratix10: add support for the 2nd bypass	2021-06-27 16:39:59 -07:00
clk-gate.c	Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner' and 'clk-qcom' into clk-next	2021-04-27 16:34:28 -07:00
clk-periph-a10.c	clk: socfpga: arria10: convert to use clk_hw	2021-03-30 19:26:26 -07:00
clk-periph-s10.c	clk: agilex/stratix10/n5x: fix how the bypass_reg is handled	2021-06-27 16:39:59 -07:00
clk-periph.c	clk: socfpga: use clk_hw_register for a5/c5	2021-03-30 19:26:26 -07:00
clk-pll-a10.c	clk: socfpga: arria10: convert to use clk_hw	2021-03-30 19:26:26 -07:00
clk-pll-s10.c	clk: socfpga: remove redundant initialization of variable div	2021-04-07 16:30:23 -07:00
clk-pll.c	clk: socfpga: clk-pll: Remove unused variable 'rc'	2021-06-27 17:33:21 -07:00
clk-s10.c	clk: agilex/stratix10: fix bypass representation	2021-06-27 16:39:59 -07:00
clk.c
clk.h
Kconfig	clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test)	2021-03-23 11:03:36 -05:00
Makefile	clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test)	2021-03-23 11:03:36 -05:00
stratix10-clk.h	clk: agilex/stratix10: add support for the 2nd bypass	2021-06-27 16:39:59 -07:00