d7e5fcd2e7
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
73 lines
2.4 KiB
C
73 lines
2.4 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv04.h"
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#include <core/device.h>
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const struct nvkm_mc_intr
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nv50_mc_intr[] = {
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{ 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */
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{ 0x00000001, NVDEV_ENGINE_MPEG },
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{ 0x00000100, NVDEV_ENGINE_FIFO },
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{ 0x00001000, NVDEV_ENGINE_GR },
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{ 0x00004000, NVDEV_ENGINE_CIPHER }, /* NV84- */
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{ 0x00008000, NVDEV_ENGINE_BSP }, /* NV84- */
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{ 0x00020000, NVDEV_ENGINE_VP }, /* NV84- */
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{ 0x00100000, NVDEV_SUBDEV_TIMER },
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{ 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */
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{ 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */
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{ 0x10000000, NVDEV_SUBDEV_BUS },
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{ 0x80000000, NVDEV_ENGINE_SW },
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{ 0x0002d101, NVDEV_SUBDEV_FB },
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{},
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};
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static void
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nv50_mc_msi_rearm(struct nvkm_mc *pmc)
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{
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struct nvkm_device *device = nv_device(pmc);
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pci_write_config_byte(device->pdev, 0x68, 0xff);
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}
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int
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nv50_mc_init(struct nvkm_object *object)
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{
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struct nv04_mc_priv *priv = (void *)object;
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nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */
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return nvkm_mc_init(&priv->base);
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}
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struct nvkm_oclass *
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nv50_mc_oclass = &(struct nvkm_mc_oclass) {
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.base.handle = NV_SUBDEV(MC, 0x50),
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.base.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv04_mc_ctor,
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.dtor = _nvkm_mc_dtor,
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.init = nv50_mc_init,
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.fini = _nvkm_mc_fini,
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},
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.intr = nv50_mc_intr,
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.msi_rearm = nv50_mc_msi_rearm,
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}.base;
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