forked from Minki/linux
5fbcf9a5c6
Resend using accessors instead of volatile qualifiers per hch comments, and easier to understand convenience macros per rja comments. Patch to apply volatile semantics when accessing MMR's in various SN files. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
208 lines
6.1 KiB
C
208 lines
6.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
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#define _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
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#include <asm/sn/tioca.h>
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/*
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* WAR enables
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* Defines for individual WARs. Each is a bitmask of applicable
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* part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B,
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* (3 << 1) == (rev A or rev B), etc
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*/
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#define TIOCA_WAR_ENABLED(pv, tioca_common) \
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((1 << tioca_common->ca_rev) & pv)
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/* TIO:ICE:FRZ:Freezer loses a PIO data ucred on PIO RD RSP with CW error */
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#define PV907908 (1 << 1)
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/* ATI config space problems after BIOS execution starts */
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#define PV908234 (1 << 1)
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/* CA:AGPDMA write request data mismatch with ABC1CL merge */
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#define PV895469 (1 << 1)
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/* TIO:CA TLB invalidate of written GART entries possibly not occuring in CA*/
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#define PV910244 (1 << 1)
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struct tioca_dmamap{
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struct list_head cad_list; /* headed by ca_list */
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dma_addr_t cad_dma_addr; /* Linux dma handle */
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uint cad_gart_entry; /* start entry in ca_gart_pagemap */
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uint cad_gart_size; /* #entries for this map */
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};
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/*
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* Kernel only fields. Prom may look at this stuff for debugging only.
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* Access this structure through the ca_kernel_private ptr.
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*/
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struct tioca_common ;
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struct tioca_kernel {
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struct tioca_common *ca_common; /* tioca this belongs to */
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struct list_head ca_list; /* list of all ca's */
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struct list_head ca_dmamaps;
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spinlock_t ca_lock; /* Kernel lock */
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cnodeid_t ca_closest_node;
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struct list_head *ca_devices; /* bus->devices */
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/*
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* General GART stuff
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*/
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uint64_t ca_ap_size; /* size of aperature in bytes */
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uint32_t ca_gart_entries; /* # uint64_t entries in gart */
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uint32_t ca_ap_pagesize; /* aperature page size in bytes */
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uint64_t ca_ap_bus_base; /* bus address of CA aperature */
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uint64_t ca_gart_size; /* gart size in bytes */
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uint64_t *ca_gart; /* gart table vaddr */
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uint64_t ca_gart_coretalk_addr; /* gart coretalk addr */
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uint8_t ca_gart_iscoherent; /* used in tioca_tlbflush */
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/* PCI GART convenience values */
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uint64_t ca_pciap_base; /* pci aperature bus base address */
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uint64_t ca_pciap_size; /* pci aperature size (bytes) */
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uint64_t ca_pcigart_base; /* gfx GART bus base address */
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uint64_t *ca_pcigart; /* gfx GART vm address */
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uint32_t ca_pcigart_entries;
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uint32_t ca_pcigart_start; /* PCI start index in ca_gart */
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void *ca_pcigart_pagemap;
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/* AGP GART convenience values */
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uint64_t ca_gfxap_base; /* gfx aperature bus base address */
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uint64_t ca_gfxap_size; /* gfx aperature size (bytes) */
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uint64_t ca_gfxgart_base; /* gfx GART bus base address */
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uint64_t *ca_gfxgart; /* gfx GART vm address */
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uint32_t ca_gfxgart_entries;
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uint32_t ca_gfxgart_start; /* agpgart start index in ca_gart */
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};
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/*
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* Common tioca info shared between kernel and prom
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*
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* DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES
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* TO THE PROM VERSION.
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*/
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struct tioca_common {
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struct pcibus_bussoft ca_common; /* common pciio header */
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uint32_t ca_rev;
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uint32_t ca_closest_nasid;
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uint64_t ca_prom_private;
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uint64_t ca_kernel_private;
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};
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/**
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* tioca_paddr_to_gart - Convert an SGI coretalk address to a CA GART entry
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* @paddr: page address to convert
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*
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* Convert a system [coretalk] address to a GART entry. GART entries are
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* formed using the following:
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*
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* data = ( (1<<63) | ( (REMAP_NODE_ID << 40) | (MD_CHIPLET_ID << 38) |
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* (REMAP_SYS_ADDR) ) >> 12 )
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*
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* DATA written to 1 GART TABLE Entry in system memory is remapped system
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* addr for 1 page
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*
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* The data is for coretalk address format right shifted 12 bits with a
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* valid bit.
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*
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* GART_TABLE_ENTRY [ 25:0 ] -- REMAP_SYS_ADDRESS[37:12].
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* GART_TABLE_ENTRY [ 27:26 ] -- SHUB MD chiplet id.
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* GART_TABLE_ENTRY [ 41:28 ] -- REMAP_NODE_ID.
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* GART_TABLE_ENTRY [ 63 ] -- Valid Bit
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*/
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static inline u64
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tioca_paddr_to_gart(unsigned long paddr)
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{
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/*
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* We are assuming right now that paddr already has the correct
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* format since the address from xtalk_dmaXXX should already have
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* NODE_ID, CHIPLET_ID, and SYS_ADDR in the correct locations.
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*/
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return ((paddr) >> 12) | (1UL << 63);
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}
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/**
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* tioca_physpage_to_gart - Map a host physical page for SGI CA based DMA
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* @page_addr: system page address to map
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*/
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static inline unsigned long
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tioca_physpage_to_gart(uint64_t page_addr)
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{
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uint64_t coretalk_addr;
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coretalk_addr = PHYS_TO_TIODMA(page_addr);
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if (!coretalk_addr) {
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return 0;
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}
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return tioca_paddr_to_gart(coretalk_addr);
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}
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/**
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* tioca_tlbflush - invalidate cached SGI CA GART TLB entries
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* @tioca_kernel: CA context
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*
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* Invalidate tlb entries for a given CA GART. Main complexity is to account
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* for revA bug.
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*/
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static inline void
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tioca_tlbflush(struct tioca_kernel *tioca_kernel)
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{
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volatile uint64_t tmp;
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volatile struct tioca *ca_base;
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struct tioca_common *tioca_common;
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tioca_common = tioca_kernel->ca_common;
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ca_base = (struct tioca *)tioca_common->ca_common.bs_base;
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/*
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* Explicit flushes not needed if GART is in cached mode
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*/
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if (tioca_kernel->ca_gart_iscoherent) {
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if (TIOCA_WAR_ENABLED(PV910244, tioca_common)) {
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/*
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* PV910244: RevA CA needs explicit flushes.
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* Need to put GART into uncached mode before
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* flushing otherwise the explicit flush is ignored.
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*
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* Alternate WAR would be to leave GART cached and
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* touch every CL aligned GART entry.
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*/
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__sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM);
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__sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
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__sn_setq_relaxed(&ca_base->ca_control2,
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(0x2ull << CA_GART_MEM_PARAM_SHFT));
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tmp = __sn_readq_relaxed(&ca_base->ca_control2);
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}
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return;
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}
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/*
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* Gart in uncached mode ... need an explicit flush.
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*/
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__sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
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tmp = __sn_readq_relaxed(&ca_base->ca_control2);
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}
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extern uint32_t tioca_gart_found;
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extern struct list_head tioca_list;
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extern int tioca_init_provider(void);
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extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
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#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
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