069d4e743c
External GIC cannot support PPI (Private Peripheral Interrupt) for ARM private timers. Thus MCT should be selected as clock event timers by default. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
84 lines
2.4 KiB
ArmAsm
84 lines
2.4 KiB
ArmAsm
/* arch/arm/mach-exynos4/include/mach/entry-macro.S
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*
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* Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for EXYNOS4 platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <asm/hardware/gic.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =gic_cpu_base_addr
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ldr \base, [\base]
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mrc p15, 0, \tmp, c0, c0, 5
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and \tmp, \tmp, #3
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cmp \tmp, #1
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addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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/*
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* The interrupt numbering scheme is defined in the
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* interrupt controller spec. To wit:
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*
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* Interrupts 0-15 are IPI
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* 16-28 are reserved
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* 29-31 are local. We allow 30 to be used for the watchdog.
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* 32-1020 are global
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* 1021-1022 are reserved
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* 1023 is "spurious" (no interrupt)
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*
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* For now, we ignore all local interrupts so only return an interrupt if it's
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* between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
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*
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* A simple read from the controller will tell us the number of the highest
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* priority enabled interrupt. We then just need to check whether it is in the
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* valid range for an IRQ (30-1020 inclusive).
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
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ldr \tmp, =1021
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #29
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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addne \irqnr, \irqnr, #32
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.endm
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/* We assume that irqstat (the raw value of the IRQ acknowledge
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* register) is preserved from the macro above.
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* If there is an IPI, we immediately signal end of interrupt on the
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* controller, since this requires the original irqstat value which
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* we won't easily be able to recreate later.
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*/
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.macro test_for_ipi, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #16
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strcc \irqstat, [\base, #GIC_CPU_EOI]
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cmpcs \irqnr, \irqnr
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.endm
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/* As above, this assumes that irqstat and base are preserved.. */
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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.endm
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