forked from Minki/linux
939d749ad6
The HDMI controller found in earlier Allwinner SoCs have slight differences between the A10, A10s, and the A31: - Need different initial values for the PLL related registers - Different behavior of the DDC and TMDS clocks - Different register layout for the DDC portion - Separate DDC parent clock on the A31 - Explicit reset control For the A31, the HDMI TMDS clock has a different value offset for the divider. The HDMI DDC block is different from the one in the other SoCs. As far as the DDC clock goes, it has no pre-divider, as it is clocked from a slower parent clock, not the TMDS clock. The divider offset from the register value is different. And the clock control register is at a different offset. A new variant data structure is created to store pointers to the above functions, structures, and the different initial values. Another flag notates whether there is a separate DDC parent clock. If not, the TMDS clock is passed to the DDC clock create function, as before. Regmap fields are used to deal with the different register layout of the DDC block. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-8-wens@csie.org
148 lines
3.3 KiB
C
148 lines
3.3 KiB
C
/*
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* Copyright (C) 2016 Free Electrons
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* Copyright (C) 2016 NextThing Co
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include "sun4i_tcon.h"
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#include "sun4i_hdmi.h"
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struct sun4i_ddc {
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struct clk_hw hw;
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struct sun4i_hdmi *hdmi;
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struct regmap_field *reg;
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u8 pre_div;
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u8 m_offset;
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};
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static inline struct sun4i_ddc *hw_to_ddc(struct clk_hw *hw)
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{
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return container_of(hw, struct sun4i_ddc, hw);
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}
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static unsigned long sun4i_ddc_calc_divider(unsigned long rate,
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unsigned long parent_rate,
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const u8 pre_div,
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const u8 m_offset,
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u8 *m, u8 *n)
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{
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unsigned long best_rate = 0;
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u8 best_m = 0, best_n = 0, _m, _n;
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for (_m = 0; _m < 8; _m++) {
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for (_n = 0; _n < 8; _n++) {
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unsigned long tmp_rate;
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tmp_rate = (((parent_rate / pre_div) / 10) >> _n) /
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(_m + m_offset);
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if (tmp_rate > rate)
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continue;
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if (abs(rate - tmp_rate) < abs(rate - best_rate)) {
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best_rate = tmp_rate;
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best_m = _m;
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best_n = _n;
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}
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}
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}
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if (m && n) {
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*m = best_m;
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*n = best_n;
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}
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return best_rate;
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}
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static long sun4i_ddc_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct sun4i_ddc *ddc = hw_to_ddc(hw);
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return sun4i_ddc_calc_divider(rate, *prate, ddc->pre_div,
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ddc->m_offset, NULL, NULL);
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}
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static unsigned long sun4i_ddc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sun4i_ddc *ddc = hw_to_ddc(hw);
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unsigned int reg;
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u8 m, n;
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regmap_field_read(ddc->reg, ®);
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m = (reg >> 3) & 0xf;
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n = reg & 0x7;
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return (((parent_rate / ddc->pre_div) / 10) >> n) /
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(m + ddc->m_offset);
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}
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static int sun4i_ddc_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct sun4i_ddc *ddc = hw_to_ddc(hw);
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u8 div_m, div_n;
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sun4i_ddc_calc_divider(rate, parent_rate, ddc->pre_div,
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ddc->m_offset, &div_m, &div_n);
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regmap_field_write(ddc->reg,
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SUN4I_HDMI_DDC_CLK_M(div_m) |
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SUN4I_HDMI_DDC_CLK_N(div_n));
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return 0;
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}
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static const struct clk_ops sun4i_ddc_ops = {
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.recalc_rate = sun4i_ddc_recalc_rate,
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.round_rate = sun4i_ddc_round_rate,
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.set_rate = sun4i_ddc_set_rate,
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};
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int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent)
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{
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struct clk_init_data init;
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struct sun4i_ddc *ddc;
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const char *parent_name;
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parent_name = __clk_get_name(parent);
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if (!parent_name)
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return -ENODEV;
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ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL);
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if (!ddc)
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return -ENOMEM;
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ddc->reg = devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
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hdmi->variant->ddc_clk_reg);
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if (IS_ERR(ddc->reg))
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return PTR_ERR(ddc->reg);
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init.name = "hdmi-ddc";
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init.ops = &sun4i_ddc_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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ddc->hdmi = hdmi;
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ddc->hw.init = &init;
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ddc->pre_div = hdmi->variant->ddc_clk_pre_divider;
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ddc->m_offset = hdmi->variant->ddc_clk_m_offset;
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hdmi->ddc_clk = devm_clk_register(hdmi->dev, &ddc->hw);
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if (IS_ERR(hdmi->ddc_clk))
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return PTR_ERR(hdmi->ddc_clk);
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return 0;
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}
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