forked from Minki/linux
1f80ba3d20
This fixes a bug in the XICS emulation on POWER9 machines which is triggered by the guest doing a H_IPI with priority = 0 (the highest priority). What happens is that the notification interrupt arrives at the destination at priority zero. The loop in scan_interrupts() sees that a priority 0 interrupt is pending, but because xc->mfrr is zero, we break out of the loop before taking the notification interrupt out of the queue and EOI-ing it. (This doesn't happen when xc->mfrr != 0; in that case we process the priority-0 notification interrupt on the first iteration of the loop, and then break out of a subsequent iteration of the loop with hirq == XICS_IPI.) To fix this, we move the prio >= xc->mfrr check down to near the end of the loop. However, there are then some other things that need to be adjusted. Since we are potentially handling the notification interrupt and also delivering an IPI to the guest in the same loop iteration, we need to update pending and handle any q->pending_count value before the xc->mfrr check, rather than at the end of the loop. Also, we need to update the queue pointers when we have processed and EOI-ed the notification interrupt, since we may not do it later. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
642 lines
16 KiB
C
642 lines
16 KiB
C
/*
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* Copyright 2017 Benjamin Herrenschmidt, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*/
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/* File to be included by other .c files */
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#define XGLUE(a,b) a##b
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#define GLUE(a,b) XGLUE(a,b)
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/* Dummy interrupt used when taking interrupts out of a queue in H_CPPR */
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#define XICS_DUMMY 1
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static void GLUE(X_PFX,ack_pending)(struct kvmppc_xive_vcpu *xc)
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{
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u8 cppr;
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u16 ack;
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/*
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* Ensure any previous store to CPPR is ordered vs.
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* the subsequent loads from PIPR or ACK.
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*/
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eieio();
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/* Perform the acknowledge OS to register cycle. */
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ack = be16_to_cpu(__x_readw(__x_tima + TM_SPC_ACK_OS_REG));
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/* Synchronize subsequent queue accesses */
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mb();
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/* XXX Check grouping level */
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/* Anything ? */
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if (!((ack >> 8) & TM_QW1_NSR_EO))
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return;
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/* Grab CPPR of the most favored pending interrupt */
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cppr = ack & 0xff;
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if (cppr < 8)
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xc->pending |= 1 << cppr;
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#ifdef XIVE_RUNTIME_CHECKS
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/* Check consistency */
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if (cppr >= xc->hw_cppr)
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pr_warn("KVM-XIVE: CPU %d odd ack CPPR, got %d at %d\n",
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smp_processor_id(), cppr, xc->hw_cppr);
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#endif
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/*
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* Update our image of the HW CPPR. We don't yet modify
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* xc->cppr, this will be done as we scan for interrupts
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* in the queues.
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*/
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xc->hw_cppr = cppr;
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}
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static u8 GLUE(X_PFX,esb_load)(struct xive_irq_data *xd, u32 offset)
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{
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u64 val;
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if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
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offset |= offset << 4;
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val =__x_readq(__x_eoi_page(xd) + offset);
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#ifdef __LITTLE_ENDIAN__
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val >>= 64-8;
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#endif
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return (u8)val;
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}
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static void GLUE(X_PFX,source_eoi)(u32 hw_irq, struct xive_irq_data *xd)
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{
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/* If the XIVE supports the new "store EOI facility, use it */
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if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
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__x_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI);
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else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW)
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opal_int_eoi(hw_irq);
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else if (xd->flags & XIVE_IRQ_FLAG_LSI) {
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/*
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* For LSIs the HW EOI cycle is used rather than PQ bits,
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* as they are automatically re-triggred in HW when still
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* pending.
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*/
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__x_readq(__x_eoi_page(xd) + XIVE_ESB_LOAD_EOI);
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} else {
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uint64_t eoi_val;
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/*
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* Otherwise for EOI, we use the special MMIO that does
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* a clear of both P and Q and returns the old Q,
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* except for LSIs where we use the "EOI cycle" special
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* load.
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*
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* This allows us to then do a re-trigger if Q was set
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* rather than synthetizing an interrupt in software
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*/
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eoi_val = GLUE(X_PFX,esb_load)(xd, XIVE_ESB_SET_PQ_00);
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/* Re-trigger if needed */
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if ((eoi_val & 1) && __x_trig_page(xd))
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__x_writeq(0, __x_trig_page(xd));
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}
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}
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enum {
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scan_fetch,
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scan_poll,
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scan_eoi,
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};
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static u32 GLUE(X_PFX,scan_interrupts)(struct kvmppc_xive_vcpu *xc,
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u8 pending, int scan_type)
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{
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u32 hirq = 0;
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u8 prio = 0xff;
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/* Find highest pending priority */
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while ((xc->mfrr != 0xff || pending != 0) && hirq == 0) {
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struct xive_q *q;
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u32 idx, toggle;
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__be32 *qpage;
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/*
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* If pending is 0 this will return 0xff which is what
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* we want
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*/
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prio = ffs(pending) - 1;
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/* Don't scan past the guest cppr */
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if (prio >= xc->cppr || prio > 7) {
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if (xc->mfrr < xc->cppr) {
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prio = xc->mfrr;
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hirq = XICS_IPI;
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}
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break;
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}
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/* Grab queue and pointers */
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q = &xc->queues[prio];
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idx = q->idx;
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toggle = q->toggle;
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/*
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* Snapshot the queue page. The test further down for EOI
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* must use the same "copy" that was used by __xive_read_eq
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* since qpage can be set concurrently and we don't want
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* to miss an EOI.
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*/
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qpage = READ_ONCE(q->qpage);
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skip_ipi:
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/*
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* Try to fetch from the queue. Will return 0 for a
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* non-queueing priority (ie, qpage = 0).
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*/
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hirq = __xive_read_eq(qpage, q->msk, &idx, &toggle);
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/*
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* If this was a signal for an MFFR change done by
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* H_IPI we skip it. Additionally, if we were fetching
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* we EOI it now, thus re-enabling reception of a new
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* such signal.
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*
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* We also need to do that if prio is 0 and we had no
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* page for the queue. In this case, we have non-queued
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* IPI that needs to be EOId.
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*
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* This is safe because if we have another pending MFRR
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* change that wasn't observed above, the Q bit will have
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* been set and another occurrence of the IPI will trigger.
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*/
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if (hirq == XICS_IPI || (prio == 0 && !qpage)) {
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if (scan_type == scan_fetch) {
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GLUE(X_PFX,source_eoi)(xc->vp_ipi,
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&xc->vp_ipi_data);
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q->idx = idx;
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q->toggle = toggle;
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}
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/* Loop back on same queue with updated idx/toggle */
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#ifdef XIVE_RUNTIME_CHECKS
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WARN_ON(hirq && hirq != XICS_IPI);
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#endif
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if (hirq)
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goto skip_ipi;
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}
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/* If it's the dummy interrupt, continue searching */
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if (hirq == XICS_DUMMY)
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goto skip_ipi;
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/* Clear the pending bit if the queue is now empty */
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if (!hirq) {
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pending &= ~(1 << prio);
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/*
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* Check if the queue count needs adjusting due to
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* interrupts being moved away.
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*/
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if (atomic_read(&q->pending_count)) {
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int p = atomic_xchg(&q->pending_count, 0);
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if (p) {
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#ifdef XIVE_RUNTIME_CHECKS
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WARN_ON(p > atomic_read(&q->count));
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#endif
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atomic_sub(p, &q->count);
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}
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}
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}
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/*
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* If the most favoured prio we found pending is less
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* favored (or equal) than a pending IPI, we return
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* the IPI instead.
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*/
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if (prio >= xc->mfrr && xc->mfrr < xc->cppr) {
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prio = xc->mfrr;
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hirq = XICS_IPI;
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break;
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}
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/* If fetching, update queue pointers */
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if (scan_type == scan_fetch) {
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q->idx = idx;
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q->toggle = toggle;
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}
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}
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/* If we are just taking a "peek", do nothing else */
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if (scan_type == scan_poll)
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return hirq;
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/* Update the pending bits */
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xc->pending = pending;
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/*
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* If this is an EOI that's it, no CPPR adjustment done here,
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* all we needed was cleanup the stale pending bits and check
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* if there's anything left.
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*/
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if (scan_type == scan_eoi)
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return hirq;
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/*
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* If we found an interrupt, adjust what the guest CPPR should
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* be as if we had just fetched that interrupt from HW.
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*
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* Note: This can only make xc->cppr smaller as the previous
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* loop will only exit with hirq != 0 if prio is lower than
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* the current xc->cppr. Thus we don't need to re-check xc->mfrr
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* for pending IPIs.
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*/
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if (hirq)
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xc->cppr = prio;
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/*
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* If it was an IPI the HW CPPR might have been lowered too much
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* as the HW interrupt we use for IPIs is routed to priority 0.
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*
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* We re-sync it here.
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*/
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if (xc->cppr != xc->hw_cppr) {
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xc->hw_cppr = xc->cppr;
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__x_writeb(xc->cppr, __x_tima + TM_QW1_OS + TM_CPPR);
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}
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return hirq;
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}
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X_STATIC unsigned long GLUE(X_PFX,h_xirr)(struct kvm_vcpu *vcpu)
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{
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struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
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u8 old_cppr;
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u32 hirq;
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pr_devel("H_XIRR\n");
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xc->GLUE(X_STAT_PFX,h_xirr)++;
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/* First collect pending bits from HW */
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GLUE(X_PFX,ack_pending)(xc);
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pr_devel(" new pending=0x%02x hw_cppr=%d cppr=%d\n",
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xc->pending, xc->hw_cppr, xc->cppr);
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/* Grab previous CPPR and reverse map it */
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old_cppr = xive_prio_to_guest(xc->cppr);
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/* Scan for actual interrupts */
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hirq = GLUE(X_PFX,scan_interrupts)(xc, xc->pending, scan_fetch);
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pr_devel(" got hirq=0x%x hw_cppr=%d cppr=%d\n",
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hirq, xc->hw_cppr, xc->cppr);
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#ifdef XIVE_RUNTIME_CHECKS
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/* That should never hit */
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if (hirq & 0xff000000)
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pr_warn("XIVE: Weird guest interrupt number 0x%08x\n", hirq);
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#endif
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/*
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* XXX We could check if the interrupt is masked here and
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* filter it. If we chose to do so, we would need to do:
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*
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* if (masked) {
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* lock();
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* if (masked) {
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* old_Q = true;
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* hirq = 0;
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* }
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* unlock();
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* }
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*/
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/* Return interrupt and old CPPR in GPR4 */
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vcpu->arch.regs.gpr[4] = hirq | (old_cppr << 24);
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return H_SUCCESS;
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}
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X_STATIC unsigned long GLUE(X_PFX,h_ipoll)(struct kvm_vcpu *vcpu, unsigned long server)
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{
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struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
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u8 pending = xc->pending;
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u32 hirq;
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pr_devel("H_IPOLL(server=%ld)\n", server);
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xc->GLUE(X_STAT_PFX,h_ipoll)++;
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/* Grab the target VCPU if not the current one */
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if (xc->server_num != server) {
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vcpu = kvmppc_xive_find_server(vcpu->kvm, server);
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if (!vcpu)
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return H_PARAMETER;
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xc = vcpu->arch.xive_vcpu;
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/* Scan all priorities */
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pending = 0xff;
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} else {
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/* Grab pending interrupt if any */
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__be64 qw1 = __x_readq(__x_tima + TM_QW1_OS);
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u8 pipr = be64_to_cpu(qw1) & 0xff;
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if (pipr < 8)
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pending |= 1 << pipr;
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}
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hirq = GLUE(X_PFX,scan_interrupts)(xc, pending, scan_poll);
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/* Return interrupt and old CPPR in GPR4 */
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vcpu->arch.regs.gpr[4] = hirq | (xc->cppr << 24);
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return H_SUCCESS;
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}
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static void GLUE(X_PFX,push_pending_to_hw)(struct kvmppc_xive_vcpu *xc)
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{
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u8 pending, prio;
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pending = xc->pending;
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if (xc->mfrr != 0xff) {
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if (xc->mfrr < 8)
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pending |= 1 << xc->mfrr;
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else
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pending |= 0x80;
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}
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if (!pending)
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return;
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prio = ffs(pending) - 1;
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__x_writeb(prio, __x_tima + TM_SPC_SET_OS_PENDING);
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}
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static void GLUE(X_PFX,scan_for_rerouted_irqs)(struct kvmppc_xive *xive,
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struct kvmppc_xive_vcpu *xc)
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{
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unsigned int prio;
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/* For each priority that is now masked */
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for (prio = xc->cppr; prio < KVMPPC_XIVE_Q_COUNT; prio++) {
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struct xive_q *q = &xc->queues[prio];
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struct kvmppc_xive_irq_state *state;
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struct kvmppc_xive_src_block *sb;
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u32 idx, toggle, entry, irq, hw_num;
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struct xive_irq_data *xd;
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__be32 *qpage;
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u16 src;
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idx = q->idx;
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toggle = q->toggle;
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qpage = READ_ONCE(q->qpage);
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if (!qpage)
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continue;
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/* For each interrupt in the queue */
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for (;;) {
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entry = be32_to_cpup(qpage + idx);
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/* No more ? */
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if ((entry >> 31) == toggle)
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break;
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irq = entry & 0x7fffffff;
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/* Skip dummies and IPIs */
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if (irq == XICS_DUMMY || irq == XICS_IPI)
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goto next;
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sb = kvmppc_xive_find_source(xive, irq, &src);
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if (!sb)
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goto next;
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state = &sb->irq_state[src];
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/* Has it been rerouted ? */
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if (xc->server_num == state->act_server)
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goto next;
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/*
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* Allright, it *has* been re-routed, kill it from
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* the queue.
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*/
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qpage[idx] = cpu_to_be32((entry & 0x80000000) | XICS_DUMMY);
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/* Find the HW interrupt */
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kvmppc_xive_select_irq(state, &hw_num, &xd);
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/* If it's not an LSI, set PQ to 11 the EOI will force a resend */
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if (!(xd->flags & XIVE_IRQ_FLAG_LSI))
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GLUE(X_PFX,esb_load)(xd, XIVE_ESB_SET_PQ_11);
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/* EOI the source */
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GLUE(X_PFX,source_eoi)(hw_num, xd);
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next:
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idx = (idx + 1) & q->msk;
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if (idx == 0)
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toggle ^= 1;
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}
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}
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}
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X_STATIC int GLUE(X_PFX,h_cppr)(struct kvm_vcpu *vcpu, unsigned long cppr)
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{
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struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
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struct kvmppc_xive *xive = vcpu->kvm->arch.xive;
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u8 old_cppr;
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pr_devel("H_CPPR(cppr=%ld)\n", cppr);
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xc->GLUE(X_STAT_PFX,h_cppr)++;
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/* Map CPPR */
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cppr = xive_prio_from_guest(cppr);
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/* Remember old and update SW state */
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old_cppr = xc->cppr;
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xc->cppr = cppr;
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/*
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* Order the above update of xc->cppr with the subsequent
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* read of xc->mfrr inside push_pending_to_hw()
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*/
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smp_mb();
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if (cppr > old_cppr) {
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/*
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* We are masking less, we need to look for pending things
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* to deliver and set VP pending bits accordingly to trigger
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* a new interrupt otherwise we might miss MFRR changes for
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* which we have optimized out sending an IPI signal.
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*/
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GLUE(X_PFX,push_pending_to_hw)(xc);
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} else {
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/*
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* We are masking more, we need to check the queue for any
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* interrupt that has been routed to another CPU, take
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* it out (replace it with the dummy) and retrigger it.
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*
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* This is necessary since those interrupts may otherwise
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* never be processed, at least not until this CPU restores
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* its CPPR.
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*
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* This is in theory racy vs. HW adding new interrupts to
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* the queue. In practice this works because the interesting
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* cases are when the guest has done a set_xive() to move the
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* interrupt away, which flushes the xive, followed by the
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* target CPU doing a H_CPPR. So any new interrupt coming into
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* the queue must still be routed to us and isn't a source
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* of concern.
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*/
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GLUE(X_PFX,scan_for_rerouted_irqs)(xive, xc);
|
|
}
|
|
|
|
/* Apply new CPPR */
|
|
xc->hw_cppr = cppr;
|
|
__x_writeb(cppr, __x_tima + TM_QW1_OS + TM_CPPR);
|
|
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
X_STATIC int GLUE(X_PFX,h_eoi)(struct kvm_vcpu *vcpu, unsigned long xirr)
|
|
{
|
|
struct kvmppc_xive *xive = vcpu->kvm->arch.xive;
|
|
struct kvmppc_xive_src_block *sb;
|
|
struct kvmppc_xive_irq_state *state;
|
|
struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
|
|
struct xive_irq_data *xd;
|
|
u8 new_cppr = xirr >> 24;
|
|
u32 irq = xirr & 0x00ffffff, hw_num;
|
|
u16 src;
|
|
int rc = 0;
|
|
|
|
pr_devel("H_EOI(xirr=%08lx)\n", xirr);
|
|
|
|
xc->GLUE(X_STAT_PFX,h_eoi)++;
|
|
|
|
xc->cppr = xive_prio_from_guest(new_cppr);
|
|
|
|
/*
|
|
* IPIs are synthetized from MFRR and thus don't need
|
|
* any special EOI handling. The underlying interrupt
|
|
* used to signal MFRR changes is EOId when fetched from
|
|
* the queue.
|
|
*/
|
|
if (irq == XICS_IPI || irq == 0) {
|
|
/*
|
|
* This barrier orders the setting of xc->cppr vs.
|
|
* subsquent test of xc->mfrr done inside
|
|
* scan_interrupts and push_pending_to_hw
|
|
*/
|
|
smp_mb();
|
|
goto bail;
|
|
}
|
|
|
|
/* Find interrupt source */
|
|
sb = kvmppc_xive_find_source(xive, irq, &src);
|
|
if (!sb) {
|
|
pr_devel(" source not found !\n");
|
|
rc = H_PARAMETER;
|
|
/* Same as above */
|
|
smp_mb();
|
|
goto bail;
|
|
}
|
|
state = &sb->irq_state[src];
|
|
kvmppc_xive_select_irq(state, &hw_num, &xd);
|
|
|
|
state->in_eoi = true;
|
|
|
|
/*
|
|
* This barrier orders both setting of in_eoi above vs,
|
|
* subsequent test of guest_priority, and the setting
|
|
* of xc->cppr vs. subsquent test of xc->mfrr done inside
|
|
* scan_interrupts and push_pending_to_hw
|
|
*/
|
|
smp_mb();
|
|
|
|
again:
|
|
if (state->guest_priority == MASKED) {
|
|
arch_spin_lock(&sb->lock);
|
|
if (state->guest_priority != MASKED) {
|
|
arch_spin_unlock(&sb->lock);
|
|
goto again;
|
|
}
|
|
pr_devel(" EOI on saved P...\n");
|
|
|
|
/* Clear old_p, that will cause unmask to perform an EOI */
|
|
state->old_p = false;
|
|
|
|
arch_spin_unlock(&sb->lock);
|
|
} else {
|
|
pr_devel(" EOI on source...\n");
|
|
|
|
/* Perform EOI on the source */
|
|
GLUE(X_PFX,source_eoi)(hw_num, xd);
|
|
|
|
/* If it's an emulated LSI, check level and resend */
|
|
if (state->lsi && state->asserted)
|
|
__x_writeq(0, __x_trig_page(xd));
|
|
|
|
}
|
|
|
|
/*
|
|
* This barrier orders the above guest_priority check
|
|
* and spin_lock/unlock with clearing in_eoi below.
|
|
*
|
|
* It also has to be a full mb() as it must ensure
|
|
* the MMIOs done in source_eoi() are completed before
|
|
* state->in_eoi is visible.
|
|
*/
|
|
mb();
|
|
state->in_eoi = false;
|
|
bail:
|
|
|
|
/* Re-evaluate pending IRQs and update HW */
|
|
GLUE(X_PFX,scan_interrupts)(xc, xc->pending, scan_eoi);
|
|
GLUE(X_PFX,push_pending_to_hw)(xc);
|
|
pr_devel(" after scan pending=%02x\n", xc->pending);
|
|
|
|
/* Apply new CPPR */
|
|
xc->hw_cppr = xc->cppr;
|
|
__x_writeb(xc->cppr, __x_tima + TM_QW1_OS + TM_CPPR);
|
|
|
|
return rc;
|
|
}
|
|
|
|
X_STATIC int GLUE(X_PFX,h_ipi)(struct kvm_vcpu *vcpu, unsigned long server,
|
|
unsigned long mfrr)
|
|
{
|
|
struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
|
|
|
|
pr_devel("H_IPI(server=%08lx,mfrr=%ld)\n", server, mfrr);
|
|
|
|
xc->GLUE(X_STAT_PFX,h_ipi)++;
|
|
|
|
/* Find target */
|
|
vcpu = kvmppc_xive_find_server(vcpu->kvm, server);
|
|
if (!vcpu)
|
|
return H_PARAMETER;
|
|
xc = vcpu->arch.xive_vcpu;
|
|
|
|
/* Locklessly write over MFRR */
|
|
xc->mfrr = mfrr;
|
|
|
|
/*
|
|
* The load of xc->cppr below and the subsequent MMIO store
|
|
* to the IPI must happen after the above mfrr update is
|
|
* globally visible so that:
|
|
*
|
|
* - Synchronize with another CPU doing an H_EOI or a H_CPPR
|
|
* updating xc->cppr then reading xc->mfrr.
|
|
*
|
|
* - The target of the IPI sees the xc->mfrr update
|
|
*/
|
|
mb();
|
|
|
|
/* Shoot the IPI if most favored than target cppr */
|
|
if (mfrr < xc->cppr)
|
|
__x_writeq(0, __x_trig_page(&xc->vp_ipi_data));
|
|
|
|
return H_SUCCESS;
|
|
}
|