b74fe7c761
The USB phys on Rockchip SoCs contain their own internal PLLs to create the 480MHz needed. Additionally this PLL output is also fed back into the core clock-controller as possible source for clocks like the GPU or others. Until now this was modelled incorrectly with a "virtual" factor clock in the clock controller. The one big caveat is that if we turn off the usb phy via the siddq signal, all analog components get turned off, including the PLLs. It is therefore possible that a source clock gets disabled without the clock driver ever knowing, possibly making the system hang. Therefore register the phy-plls as real clocks that the clock driver can then reference again normally, making the clock hirarchy finally reflect the actual hardware. The phy-ops get converted to simply turning that new clock on and off which in turn controls the siddq signal of the phy. Through this the driver gains handling for platform-specific data, to handle the phy->clock name association. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
42 lines
1004 B
Plaintext
42 lines
1004 B
Plaintext
ROCKCHIP USB2 PHY
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Required properties:
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- compatible: matching the soc type, one of
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"rockchip,rk3066a-usb-phy"
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"rockchip,rk3188-usb-phy"
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"rockchip,rk3288-usb-phy"
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- rockchip,grf : phandle to the syscon managing the "general
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register files"
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- #address-cells: should be 1
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- #size-cells: should be 0
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Sub-nodes:
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Each PHY should be represented as a sub-node.
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Sub-nodes
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required properties:
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- #phy-cells: should be 0
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- reg: PHY configure reg address offset in GRF
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"0x320" - for PHY attach to OTG controller
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"0x334" - for PHY attach to HOST0 controller
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"0x348" - for PHY attach to HOST1 controller
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Optional Properties:
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- clocks : phandle + clock specifier for the phy clocks
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- clock-names: string, clock name, must be "phyclk"
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- #clock-cells: for users of the phy-pll, should be 0
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Example:
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usbphy: phy {
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compatible = "rockchip,rk3288-usb-phy";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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usbphy0: usb-phy0 {
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#phy-cells = <0>;
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reg = <0x320>;
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};
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};
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