forked from Minki/linux
857a26222f
User Accelerated Function Unit sub feature exposes the MMIO region of the AFU. After valid PR bitstream is programmed and the port is enabled, then this MMIO region could be accessed. This patch adds support to enumerate the AFU MMIO region and expose it to userspace via mmap file operation. Below interfaces are exposed to user: Sysfs interface: * /sys/class/fpga_region/<regionX>/<dfl-port.x>/afu_id Read-only. Indicate which PR bitstream is programmed to this AFU. Ioctl interfaces: * DFL_FPGA_PORT_GET_INFO Provide info to userspace on the number of supported region. Only UAFU region is supported now. * DFL_FPGA_PORT_GET_REGION_INFO Provide region information, including access permission, region size, offset from the start of device fd. Signed-off-by: Tim Whisonant <tim.whisonant@intel.com> Signed-off-by: Enno Luebbers <enno.luebbers@intel.com> Signed-off-by: Shiva Rao <shiva.rao@intel.com> Signed-off-by: Christopher Rauer <christopher.rauer@intel.com> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
45 lines
1.6 KiB
Makefile
45 lines
1.6 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the fpga framework and fpga manager drivers.
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#
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# Core FPGA Manager Framework
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obj-$(CONFIG_FPGA) += fpga-mgr.o
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# FPGA Manager Drivers
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obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
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obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
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obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
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obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
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obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
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obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
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obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
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obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
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obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
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obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
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obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
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# FPGA Bridge Drivers
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obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
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obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
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obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
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obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
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# High Level Interfaces
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obj-$(CONFIG_FPGA_REGION) += fpga-region.o
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obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
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# FPGA Device Feature List Support
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obj-$(CONFIG_FPGA_DFL) += dfl.o
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obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
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obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o
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obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o
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obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o
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obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o
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dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
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dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o
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# Drivers for FPGAs which implement DFL
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obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
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