forked from Minki/linux
f54e9f2be3
Depending on conversion mode used, the ADC clock (ADCK) needs to be below a maximum frequency. According to Vybrid's data sheet this is 20MHz for the low power conversion mode. The ADC clock is depending on input clock, which is the bus clock by default. Vybrid SoC are typically clocked at at 400MHz or 500MHz, which leads to 66MHz or 83MHz bus clock respectively. Hence, a divider of 8 is required to stay below the specified maximum clock of 20MHz. Due to the different bus clock speeds, the resulting sampling frequency is not static. Hence use the ADC clock and calculate the actual available sampling frequency dynamically. This fixes bogous values observed on some 500MHz clocked Vybrid SoC. The resulting value usually showed Bit 9 being stuck at 1, or 0, which lead to a value of +/-512. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Fugang Duan <B38611@freescale.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org> |
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| .. | ||
| ad799x.c | ||
| ad7266.c | ||
| ad7291.c | ||
| ad7298.c | ||
| ad7476.c | ||
| ad7791.c | ||
| ad7793.c | ||
| ad7887.c | ||
| ad7923.c | ||
| ad_sigma_delta.c | ||
| at91_adc.c | ||
| axp288_adc.c | ||
| cc10001_adc.c | ||
| exynos_adc.c | ||
| Kconfig | ||
| lp8788_adc.c | ||
| Makefile | ||
| max1027.c | ||
| max1363.c | ||
| mcp320x.c | ||
| mcp3422.c | ||
| men_z188_adc.c | ||
| nau7802.c | ||
| qcom-spmi-iadc.c | ||
| qcom-spmi-vadc.c | ||
| rockchip_saradc.c | ||
| ti_am335x_adc.c | ||
| ti-adc081c.c | ||
| ti-adc128s052.c | ||
| twl4030-madc.c | ||
| twl6030-gpadc.c | ||
| vf610_adc.c | ||
| viperboard_adc.c | ||
| xilinx-xadc-core.c | ||
| xilinx-xadc-events.c | ||
| xilinx-xadc.h | ||