831d828bf2
There are two kinds of dsaf device in hns, one is for service ports,
contains crossbar in it, can work under different mode. Another is for
debug port, only can work under "single-port" mode. The current code only
declared a dsaf device for both service ports and debug ports. This patch
separate it to three platform devices.
Here is the diagram of all port in one platform device(old):
CPU
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| DSAF(one platform device)
-------------------------------------------------------------- /
| | | | | /
| PPE PPE PPE | /
| | | | | /
| | | | | /
| crossbar | | | /
| | | | |/
| ----------------------------------- | | |
| | | | | | | | | |
| | | | | | | | | |
| MAC MAC MAC MAC MAC MAC MAC MAC |
| | | | | | | | | |
--------------------------------------------------------------
| | | | | | | |
PHY PHY PHY PHY PHY PHY PHY PHY
Here is the diagram of separate all ports to three platform(new):
CPU
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-----------------------------------
| | |
---------------------------------------------- --------- ---------
| | | | | | | |
| PPE | | PPE | | PPE |
| | | | | | | | |
| | | | | | | | |
| crossbar | | | | | | |
| | | | | | | | |
| ---------------------------------- | | | | | | |
| | | | | | | | | | | | | |
| | | | | | | | | | | | | |
| MAC MAC MAC MAC MAC MAC | | MAC | | MAC |
| | | | | | | | | | | | | |
---------------------------------------------- --------- ---------
| | | | | | \ / | / |
PHY PHY PHY PHY PHY PHY \ / PHY / PHY
\ / /
\ / /
DSAF(three platform device)
Signed-off-by: Daode Huang <huangdaode@hisilicon.com>
Signed-off-by: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
620 lines
18 KiB
C
620 lines
18 KiB
C
/*
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* Copyright (c) 2014-2015 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include "hns_dsaf_ppe.h"
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void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value)
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{
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dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value);
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}
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void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
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const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM])
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{
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u32 key_item;
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for (key_item = 0; key_item < HNS_PPEV2_RSS_KEY_NUM; key_item++)
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dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4,
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rss_key[key_item]);
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}
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void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
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const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE])
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{
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int i;
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int reg_value;
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for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) {
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reg_value = dsaf_read_dev(ppe_cb,
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PPEV2_INDRECTION_TBL_REG + i * 0x4);
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dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,
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PPEV2_CFG_RSS_TBL_4N0_S,
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rss_tab[i * 4 + 0] & 0x1F);
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dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,
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PPEV2_CFG_RSS_TBL_4N1_S,
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rss_tab[i * 4 + 1] & 0x1F);
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dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,
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PPEV2_CFG_RSS_TBL_4N2_S,
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rss_tab[i * 4 + 2] & 0x1F);
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dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,
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PPEV2_CFG_RSS_TBL_4N3_S,
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rss_tab[i * 4 + 3] & 0x1F);
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dsaf_write_dev(
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ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value);
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}
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}
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static void __iomem *
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hns_ppe_common_get_ioaddr(struct ppe_common_cb *ppe_common)
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{
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return ppe_common->dsaf_dev->ppe_base + PPE_COMMON_REG_OFFSET;
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}
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/**
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* hns_ppe_common_get_cfg - get ppe common config
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* @dsaf_dev: dasf device
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* comm_index: common index
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* retuen 0 - success , negative --fail
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*/
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int hns_ppe_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index)
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{
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struct ppe_common_cb *ppe_common;
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int ppe_num;
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if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
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ppe_num = HNS_PPE_SERVICE_NW_ENGINE_NUM;
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else
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ppe_num = HNS_PPE_DEBUG_NW_ENGINE_NUM;
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ppe_common = devm_kzalloc(dsaf_dev->dev, sizeof(*ppe_common) +
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ppe_num * sizeof(struct hns_ppe_cb), GFP_KERNEL);
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if (!ppe_common)
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return -ENOMEM;
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ppe_common->ppe_num = ppe_num;
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ppe_common->dsaf_dev = dsaf_dev;
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ppe_common->comm_index = comm_index;
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if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
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ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE;
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else
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ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG;
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ppe_common->dev = dsaf_dev->dev;
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ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common);
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dsaf_dev->ppe_common[comm_index] = ppe_common;
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return 0;
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}
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void hns_ppe_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index)
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{
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dsaf_dev->ppe_common[comm_index] = NULL;
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}
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static void __iomem *hns_ppe_get_iobase(struct ppe_common_cb *ppe_common,
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int ppe_idx)
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{
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return ppe_common->dsaf_dev->ppe_base + ppe_idx * PPE_REG_OFFSET;
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}
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static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common)
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{
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u32 i;
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struct hns_ppe_cb *ppe_cb;
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u32 ppe_num = ppe_common->ppe_num;
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for (i = 0; i < ppe_num; i++) {
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ppe_cb = &ppe_common->ppe_cb[i];
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ppe_cb->dev = ppe_common->dev;
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ppe_cb->next = NULL;
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ppe_cb->ppe_common_cb = ppe_common;
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ppe_cb->index = i;
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ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i);
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ppe_cb->virq = 0;
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}
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}
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static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb)
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{
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dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG,
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PPE_CNT_CLR_CE_B, 1);
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}
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static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en)
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{
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dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en);
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}
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/**
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* hns_ppe_checksum_hw - set ppe checksum caculate
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* @ppe_device: ppe device
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* @value: value
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*/
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static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value)
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{
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dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG,
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0xfffffff, 0, value);
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}
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static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common,
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enum ppe_qid_mode qid_mdoe)
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{
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dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG,
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PPE_CFG_QID_MODE_CF_QID_MODE_M,
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PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe);
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}
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/**
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* hns_ppe_set_qid - set ppe qid
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* @ppe_common: ppe common device
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* @qid: queue id
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*/
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static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid)
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{
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u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
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if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
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PPE_CFG_QID_MODE_DEF_QID_S)) {
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dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
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PPE_CFG_QID_MODE_DEF_QID_S, qid);
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dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod);
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}
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}
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/**
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* hns_ppe_set_port_mode - set port mode
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* @ppe_device: ppe device
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* @mode: port mode
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*/
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static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb,
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enum ppe_port_mode mode)
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{
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dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode);
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}
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/**
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* hns_ppe_common_init_hw - init ppe common device
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* @ppe_common: ppe common device
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*
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* Return 0 on success, negative on failure
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*/
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static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common)
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{
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enum ppe_qid_mode qid_mode;
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enum dsaf_mode dsaf_mode = ppe_common->dsaf_dev->dsaf_mode;
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hns_ppe_com_srst(ppe_common, 0);
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mdelay(100);
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hns_ppe_com_srst(ppe_common, 1);
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mdelay(100);
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if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) {
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switch (dsaf_mode) {
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case DSAF_MODE_ENABLE_FIX:
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case DSAF_MODE_DISABLE_FIX:
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qid_mode = PPE_QID_MODE0;
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hns_ppe_set_qid(ppe_common, 0);
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break;
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case DSAF_MODE_ENABLE_0VM:
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case DSAF_MODE_DISABLE_2PORT_64VM:
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qid_mode = PPE_QID_MODE3;
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break;
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case DSAF_MODE_ENABLE_8VM:
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case DSAF_MODE_DISABLE_2PORT_16VM:
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qid_mode = PPE_QID_MODE4;
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break;
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case DSAF_MODE_ENABLE_16VM:
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case DSAF_MODE_DISABLE_6PORT_0VM:
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qid_mode = PPE_QID_MODE5;
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break;
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case DSAF_MODE_ENABLE_32VM:
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case DSAF_MODE_DISABLE_6PORT_16VM:
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qid_mode = PPE_QID_MODE2;
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break;
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case DSAF_MODE_ENABLE_128VM:
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case DSAF_MODE_DISABLE_6PORT_4VM:
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qid_mode = PPE_QID_MODE1;
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break;
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case DSAF_MODE_DISABLE_2PORT_8VM:
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qid_mode = PPE_QID_MODE7;
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break;
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case DSAF_MODE_DISABLE_6PORT_2VM:
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qid_mode = PPE_QID_MODE6;
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break;
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default:
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dev_err(ppe_common->dev,
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"get ppe queue mode failed! dsaf_mode=%d\n",
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dsaf_mode);
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return -EINVAL;
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}
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hns_ppe_set_qid_mode(ppe_common, qid_mode);
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}
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dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG,
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PPE_COMMON_CNT_CLR_CE_B, 1);
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return 0;
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}
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/*clr ppe exception irq*/
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static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en)
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{
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u32 clr_vlue = 0xfffffffful;
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u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/
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u32 vld_msk = 0;
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/*only care bit 0,1,7*/
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dsaf_set_bit(vld_msk, 0, 1);
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dsaf_set_bit(vld_msk, 1, 1);
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dsaf_set_bit(vld_msk, 7, 1);
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/*clr sts**/
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dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);
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/*for some reserved bits, so set 0**/
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dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
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}
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/**
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* ppe_init_hw - init ppe
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* @ppe_cb: ppe device
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*/
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static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb)
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{
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struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb;
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u32 port = ppe_cb->index;
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struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev;
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int i;
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/* get default RSS key */
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netdev_rss_key_fill(ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE);
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hns_ppe_srst_by_port(dsaf_dev, port, 0);
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mdelay(10);
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hns_ppe_srst_by_port(dsaf_dev, port, 1);
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/* clr and msk except irq*/
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hns_ppe_exc_irq_en(ppe_cb, 0);
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if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) {
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hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE);
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dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0);
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} else {
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hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE);
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}
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hns_ppe_checksum_hw(ppe_cb, 0xffffffff);
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hns_ppe_cnt_clr_ce(ppe_cb);
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if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
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hns_ppe_set_vlan_strip(ppe_cb, 0);
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dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG,
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HNS_PPEV2_MAX_FRAME_LEN);
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/* set default RSS key in h/w */
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hns_ppe_set_rss_key(ppe_cb, ppe_cb->rss_key);
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/* Set default indrection table in h/w */
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for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++)
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ppe_cb->rss_indir_table[i] = i;
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hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table);
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}
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}
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/**
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* ppe_uninit_hw - uninit ppe
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* @ppe_device: ppe device
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*/
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static void hns_ppe_uninit_hw(struct hns_ppe_cb *ppe_cb)
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{
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u32 port;
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if (ppe_cb->ppe_common_cb) {
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port = ppe_cb->index;
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hns_ppe_srst_by_port(ppe_cb->ppe_common_cb->dsaf_dev, port, 0);
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}
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}
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void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common)
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{
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u32 i;
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for (i = 0; i < ppe_common->ppe_num; i++) {
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if (ppe_common->dsaf_dev->mac_cb[i])
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hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]);
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memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb));
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}
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}
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void hns_ppe_uninit(struct dsaf_device *dsaf_dev)
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{
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u32 i;
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for (i = 0; i < HNS_PPE_COM_NUM; i++) {
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if (dsaf_dev->ppe_common[i])
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hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]);
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hns_rcb_common_free_cfg(dsaf_dev, i);
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hns_ppe_common_free_cfg(dsaf_dev, i);
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}
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}
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/**
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* hns_ppe_reset - reinit ppe/rcb hw
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* @dsaf_dev: dasf device
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* retuen void
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*/
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void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index)
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{
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u32 i;
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int ret;
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struct ppe_common_cb *ppe_common;
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ppe_common = dsaf_dev->ppe_common[ppe_common_index];
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ret = hns_ppe_common_init_hw(ppe_common);
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if (ret)
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return;
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for (i = 0; i < ppe_common->ppe_num; i++) {
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/* We only need to initiate ppe when the port exists */
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if (dsaf_dev->mac_cb[i])
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hns_ppe_init_hw(&ppe_common->ppe_cb[i]);
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}
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ret = hns_rcb_common_init_hw(dsaf_dev->rcb_common[ppe_common_index]);
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if (ret)
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return;
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hns_rcb_common_init_commit_hw(dsaf_dev->rcb_common[ppe_common_index]);
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}
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void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb)
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{
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struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
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hw_stats->rx_pkts_from_sw
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+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
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hw_stats->rx_pkts
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+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
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hw_stats->rx_drop_no_bd
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+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
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hw_stats->rx_alloc_buf_fail
|
|
+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
|
|
hw_stats->rx_alloc_buf_wait
|
|
+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
|
|
hw_stats->rx_drop_no_buf
|
|
+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
|
|
hw_stats->rx_err_fifo_full
|
|
+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
|
|
|
|
hw_stats->tx_bd_form_rcb
|
|
+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
|
|
hw_stats->tx_pkts_from_rcb
|
|
+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
|
|
hw_stats->tx_pkts
|
|
+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
|
|
hw_stats->tx_err_fifo_empty
|
|
+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
|
|
hw_stats->tx_err_checksum
|
|
+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
|
|
}
|
|
|
|
int hns_ppe_get_sset_count(int stringset)
|
|
{
|
|
if (stringset == ETH_SS_STATS)
|
|
return ETH_PPE_STATIC_NUM;
|
|
return 0;
|
|
}
|
|
|
|
int hns_ppe_get_regs_count(void)
|
|
{
|
|
return ETH_PPE_DUMP_NUM;
|
|
}
|
|
|
|
/**
|
|
* ppe_get_strings - get ppe srting
|
|
* @ppe_device: ppe device
|
|
* @stringset: string set type
|
|
* @data: output string
|
|
*/
|
|
void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data)
|
|
{
|
|
char *buff = (char *)data;
|
|
int index = ppe_cb->index;
|
|
|
|
snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_sw_pkt", index);
|
|
buff = buff + ETH_GSTRING_LEN;
|
|
snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_ok", index);
|
|
buff = buff + ETH_GSTRING_LEN;
|
|
snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_drop_pkt_no_bd", index);
|
|
buff = buff + ETH_GSTRING_LEN;
|
|
snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_fail", index);
|
|
buff = buff + ETH_GSTRING_LEN;
|
|
snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_wait", index);
|
|
buff = buff + ETH_GSTRING_LEN;
|
|
snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_drop_no_buf", index);
|
|
buff = buff + ETH_GSTRING_LEN;
|
|
snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_err_fifo_full", index);
|
|
buff = buff + ETH_GSTRING_LEN;
|
|
|
|
snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_bd", index);
|
|
buff = buff + ETH_GSTRING_LEN;
|
|
snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt", index);
|
|
buff = buff + ETH_GSTRING_LEN;
|
|
snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_ok", index);
|
|
buff = buff + ETH_GSTRING_LEN;
|
|
snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_fifo_empty", index);
|
|
buff = buff + ETH_GSTRING_LEN;
|
|
snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_csum_fail", index);
|
|
}
|
|
|
|
void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data)
|
|
{
|
|
u64 *regs_buff = data;
|
|
struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
|
|
|
|
regs_buff[0] = hw_stats->rx_pkts_from_sw;
|
|
regs_buff[1] = hw_stats->rx_pkts;
|
|
regs_buff[2] = hw_stats->rx_drop_no_bd;
|
|
regs_buff[3] = hw_stats->rx_alloc_buf_fail;
|
|
regs_buff[4] = hw_stats->rx_alloc_buf_wait;
|
|
regs_buff[5] = hw_stats->rx_drop_no_buf;
|
|
regs_buff[6] = hw_stats->rx_err_fifo_full;
|
|
|
|
regs_buff[7] = hw_stats->tx_bd_form_rcb;
|
|
regs_buff[8] = hw_stats->tx_pkts_from_rcb;
|
|
regs_buff[9] = hw_stats->tx_pkts;
|
|
regs_buff[10] = hw_stats->tx_err_fifo_empty;
|
|
regs_buff[11] = hw_stats->tx_err_checksum;
|
|
}
|
|
|
|
/**
|
|
* hns_ppe_init - init ppe device
|
|
* @dsaf_dev: dasf device
|
|
* retuen 0 - success , negative --fail
|
|
*/
|
|
int hns_ppe_init(struct dsaf_device *dsaf_dev)
|
|
{
|
|
int i, k;
|
|
int ret;
|
|
|
|
for (i = 0; i < HNS_PPE_COM_NUM; i++) {
|
|
ret = hns_ppe_common_get_cfg(dsaf_dev, i);
|
|
if (ret)
|
|
goto get_ppe_cfg_fail;
|
|
|
|
ret = hns_rcb_common_get_cfg(dsaf_dev, i);
|
|
if (ret)
|
|
goto get_rcb_cfg_fail;
|
|
|
|
hns_ppe_get_cfg(dsaf_dev->ppe_common[i]);
|
|
|
|
hns_rcb_get_cfg(dsaf_dev->rcb_common[i]);
|
|
}
|
|
|
|
for (i = 0; i < HNS_PPE_COM_NUM; i++)
|
|
hns_ppe_reset_common(dsaf_dev, i);
|
|
|
|
return 0;
|
|
|
|
get_rcb_cfg_fail:
|
|
hns_ppe_common_free_cfg(dsaf_dev, i);
|
|
get_ppe_cfg_fail:
|
|
for (k = i - 1; k >= 0; k--) {
|
|
hns_rcb_common_free_cfg(dsaf_dev, k);
|
|
hns_ppe_common_free_cfg(dsaf_dev, k);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data)
|
|
{
|
|
struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb;
|
|
u32 *regs = data;
|
|
u32 i;
|
|
u32 offset;
|
|
|
|
/* ppe common registers */
|
|
regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
|
|
regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG);
|
|
regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG);
|
|
regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG);
|
|
regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG);
|
|
|
|
for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) {
|
|
offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i;
|
|
regs[5 + i] = dsaf_read_dev(ppe_common, offset);
|
|
offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i;
|
|
regs[5 + i + DSAF_TOTAL_QUEUE_NUM]
|
|
= dsaf_read_dev(ppe_common, offset);
|
|
offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i;
|
|
regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2]
|
|
= dsaf_read_dev(ppe_common, offset);
|
|
offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i;
|
|
regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3]
|
|
= dsaf_read_dev(ppe_common, offset);
|
|
}
|
|
|
|
/* mark end of ppe regs */
|
|
for (i = 521; i < 524; i++)
|
|
regs[i] = 0xeeeeeeee;
|
|
|
|
/* ppe channel registers */
|
|
regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG);
|
|
regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG);
|
|
regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG);
|
|
regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG);
|
|
regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG);
|
|
regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG);
|
|
regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG);
|
|
regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG);
|
|
|
|
regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG);
|
|
regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG);
|
|
regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG);
|
|
regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG);
|
|
regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG);
|
|
regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG);
|
|
regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG);
|
|
|
|
regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG);
|
|
regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG);
|
|
regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG);
|
|
regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG);
|
|
|
|
regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG);
|
|
regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG);
|
|
|
|
/* ppe static */
|
|
regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
|
|
regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
|
|
regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
|
|
regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
|
|
regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
|
|
regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
|
|
regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
|
|
regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
|
|
regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
|
|
regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
|
|
regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
|
|
regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
|
|
|
|
regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG);
|
|
regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG);
|
|
regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG);
|
|
regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG);
|
|
regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG);
|
|
regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG);
|
|
regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG);
|
|
regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG);
|
|
regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG);
|
|
regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG);
|
|
regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG);
|
|
regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG);
|
|
regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG);
|
|
regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG);
|
|
|
|
/* mark end of ppe regs */
|
|
for (i = 572; i < 576; i++)
|
|
regs[i] = 0xeeeeeeee;
|
|
}
|