forked from Minki/linux
826c71a065
Only a few files really need that platform header. When later splitting omap_mmc_platform_data into omap_mmc and omap_mmc_hs, those files declaring an hs mmc platform data will have to change the platform include, which is a good sanity check. Also removing omap242x_init_mmc, which is not used anywhere, checked with grep. Signed-off-by: Andreas Fenkart <afenkart@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
1471 lines
37 KiB
C
1471 lines
37 KiB
C
/*
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*
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* Copyright (C) 2013 Texas Instruments Incorporated
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*
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* Hwmod common for AM335x and AM43x
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/platform_data/gpio-omap.h>
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#include <linux/platform_data/mmc-omap.h>
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#include <linux/platform_data/spi-omap2-mcspi.h>
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#include "omap_hwmod.h"
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#include "i2c.h"
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#include "wd_timer.h"
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#include "cm33xx.h"
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#include "prm33xx.h"
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#include "omap_hwmod_33xx_43xx_common_data.h"
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#include "prcm43xx.h"
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#include "common.h"
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#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
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#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
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#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
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/*
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* 'l3' class
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* instance(s): l3_main, l3_s, l3_instr
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*/
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static struct omap_hwmod_class am33xx_l3_hwmod_class = {
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.name = "l3",
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};
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struct omap_hwmod am33xx_l3_main_hwmod = {
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.name = "l3_main",
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.class = &am33xx_l3_hwmod_class,
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.clkdm_name = "l3_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "l3_gclk",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* l3_s */
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struct omap_hwmod am33xx_l3_s_hwmod = {
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.name = "l3_s",
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.class = &am33xx_l3_hwmod_class,
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.clkdm_name = "l3s_clkdm",
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};
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/* l3_instr */
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struct omap_hwmod am33xx_l3_instr_hwmod = {
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.name = "l3_instr",
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.class = &am33xx_l3_hwmod_class,
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.clkdm_name = "l3_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "l3_gclk",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'l4' class
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* instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
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*/
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struct omap_hwmod_class am33xx_l4_hwmod_class = {
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.name = "l4",
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};
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/* l4_ls */
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struct omap_hwmod am33xx_l4_ls_hwmod = {
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.name = "l4_ls",
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.class = &am33xx_l4_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* l4_wkup */
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struct omap_hwmod am33xx_l4_wkup_hwmod = {
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.name = "l4_wkup",
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.class = &am33xx_l4_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'mpu' class
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*/
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static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
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.name = "mpu",
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};
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struct omap_hwmod am33xx_mpu_hwmod = {
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.name = "mpu",
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.class = &am33xx_mpu_hwmod_class,
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.clkdm_name = "mpu_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "dpll_mpu_m2_ck",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'wakeup m3' class
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* Wakeup controller sub-system under wakeup domain
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*/
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struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
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.name = "wkup_m3",
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};
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/*
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* 'pru-icss' class
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* Programmable Real-Time Unit and Industrial Communication Subsystem
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*/
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static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
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.name = "pruss",
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};
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static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
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{ .name = "pruss", .rst_shift = 1 },
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};
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/* pru-icss */
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/* Pseudo hwmod for reset control purpose only */
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struct omap_hwmod am33xx_pruss_hwmod = {
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.name = "pruss",
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.class = &am33xx_pruss_hwmod_class,
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.clkdm_name = "pruss_ocp_clkdm",
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.main_clk = "pruss_ocp_gclk",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.rst_lines = am33xx_pruss_resets,
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.rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
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};
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/* gfx */
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/* Pseudo hwmod for reset control purpose only */
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static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
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.name = "gfx",
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};
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static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
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{ .name = "gfx", .rst_shift = 0, .st_shift = 0},
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};
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struct omap_hwmod am33xx_gfx_hwmod = {
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.name = "gfx",
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.class = &am33xx_gfx_hwmod_class,
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.clkdm_name = "gfx_l3_clkdm",
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.main_clk = "gfx_fck_div_ck",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.rst_lines = am33xx_gfx_resets,
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.rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
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};
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/*
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* 'prcm' class
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* power and reset manager (whole prcm infrastructure)
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*/
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static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
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.name = "prcm",
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};
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/* prcm */
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struct omap_hwmod am33xx_prcm_hwmod = {
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.name = "prcm",
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.class = &am33xx_prcm_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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};
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/*
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* 'aes0' class
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*/
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static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
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.rev_offs = 0x80,
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.sysc_offs = 0x84,
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.syss_offs = 0x88,
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.sysc_flags = SYSS_HAS_RESET_STATUS,
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};
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static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
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.name = "aes0",
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.sysc = &am33xx_aes0_sysc,
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};
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struct omap_hwmod am33xx_aes0_hwmod = {
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.name = "aes",
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.class = &am33xx_aes0_hwmod_class,
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.clkdm_name = "l3_clkdm",
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.main_clk = "aes0_fck",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* sha0 HIB2 (the 'P' (public) device) */
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static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
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.rev_offs = 0x100,
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.sysc_offs = 0x110,
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.syss_offs = 0x114,
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.sysc_flags = SYSS_HAS_RESET_STATUS,
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};
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static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
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.name = "sha0",
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.sysc = &am33xx_sha0_sysc,
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};
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struct omap_hwmod am33xx_sha0_hwmod = {
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.name = "sham",
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.class = &am33xx_sha0_hwmod_class,
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.clkdm_name = "l3_clkdm",
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.main_clk = "l3_gclk",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* ocmcram */
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static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
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.name = "ocmcram",
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};
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struct omap_hwmod am33xx_ocmcram_hwmod = {
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.name = "ocmcram",
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.class = &am33xx_ocmcram_hwmod_class,
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.clkdm_name = "l3_clkdm",
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.flags = HWMOD_INIT_NO_IDLE,
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.main_clk = "l3_gclk",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* 'smartreflex' class */
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static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
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.name = "smartreflex",
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};
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/* smartreflex0 */
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struct omap_hwmod am33xx_smartreflex0_hwmod = {
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.name = "smartreflex0",
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.class = &am33xx_smartreflex_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.main_clk = "smartreflex0_fck",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* smartreflex1 */
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struct omap_hwmod am33xx_smartreflex1_hwmod = {
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.name = "smartreflex1",
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.class = &am33xx_smartreflex_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.main_clk = "smartreflex1_fck",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'control' module class
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*/
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struct omap_hwmod_class am33xx_control_hwmod_class = {
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.name = "control",
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};
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/*
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* 'cpgmac' class
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* cpsw/cpgmac sub system
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*/
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static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x8,
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.syss_offs = 0x4,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
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SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
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MSTANDBY_NO),
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.sysc_fields = &omap_hwmod_sysc_type3,
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};
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static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
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.name = "cpgmac0",
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.sysc = &am33xx_cpgmac_sysc,
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};
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struct omap_hwmod am33xx_cpgmac0_hwmod = {
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.name = "cpgmac0",
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.class = &am33xx_cpgmac0_hwmod_class,
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.clkdm_name = "cpsw_125mhz_clkdm",
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.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
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.main_clk = "cpsw_125mhz_gclk",
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.mpu_rt_idx = 1,
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* mdio class
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*/
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static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
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.name = "davinci_mdio",
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};
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struct omap_hwmod am33xx_mdio_hwmod = {
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.name = "davinci_mdio",
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.class = &am33xx_mdio_hwmod_class,
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.clkdm_name = "cpsw_125mhz_clkdm",
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.main_clk = "cpsw_125mhz_gclk",
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};
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/*
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* dcan class
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*/
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static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
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.name = "d_can",
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};
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/* dcan0 */
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struct omap_hwmod am33xx_dcan0_hwmod = {
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.name = "d_can0",
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.class = &am33xx_dcan_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "dcan0_fck",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* dcan1 */
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struct omap_hwmod am33xx_dcan1_hwmod = {
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.name = "d_can1",
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.class = &am33xx_dcan_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "dcan1_fck",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* elm */
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static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
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SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class am33xx_elm_hwmod_class = {
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.name = "elm",
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.sysc = &am33xx_elm_sysc,
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};
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struct omap_hwmod am33xx_elm_hwmod = {
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.name = "elm",
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.class = &am33xx_elm_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* pwmss */
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static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x4,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
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MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
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.name = "epwmss",
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.sysc = &am33xx_epwmss_sysc,
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};
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static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
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.name = "ecap",
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};
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static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
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.name = "eqep",
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};
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struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
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.name = "ehrpwm",
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};
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/* epwmss0 */
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struct omap_hwmod am33xx_epwmss0_hwmod = {
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.name = "epwmss0",
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.class = &am33xx_epwmss_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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.prcm = {
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.omap4 = {
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* ecap0 */
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struct omap_hwmod am33xx_ecap0_hwmod = {
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.name = "ecap0",
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.class = &am33xx_ecap_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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};
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/* eqep0 */
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struct omap_hwmod am33xx_eqep0_hwmod = {
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.name = "eqep0",
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.class = &am33xx_eqep_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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};
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/* ehrpwm0 */
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struct omap_hwmod am33xx_ehrpwm0_hwmod = {
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.name = "ehrpwm0",
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.class = &am33xx_ehrpwm_hwmod_class,
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.clkdm_name = "l4ls_clkdm",
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.main_clk = "l4ls_gclk",
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};
|
|
|
|
/* epwmss1 */
|
|
struct omap_hwmod am33xx_epwmss1_hwmod = {
|
|
.name = "epwmss1",
|
|
.class = &am33xx_epwmss_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* ecap1 */
|
|
struct omap_hwmod am33xx_ecap1_hwmod = {
|
|
.name = "ecap1",
|
|
.class = &am33xx_ecap_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
};
|
|
|
|
/* eqep1 */
|
|
struct omap_hwmod am33xx_eqep1_hwmod = {
|
|
.name = "eqep1",
|
|
.class = &am33xx_eqep_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
};
|
|
|
|
/* ehrpwm1 */
|
|
struct omap_hwmod am33xx_ehrpwm1_hwmod = {
|
|
.name = "ehrpwm1",
|
|
.class = &am33xx_ehrpwm_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
};
|
|
|
|
/* epwmss2 */
|
|
struct omap_hwmod am33xx_epwmss2_hwmod = {
|
|
.name = "epwmss2",
|
|
.class = &am33xx_epwmss_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* ecap2 */
|
|
struct omap_hwmod am33xx_ecap2_hwmod = {
|
|
.name = "ecap2",
|
|
.class = &am33xx_ecap_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
};
|
|
|
|
/* eqep2 */
|
|
struct omap_hwmod am33xx_eqep2_hwmod = {
|
|
.name = "eqep2",
|
|
.class = &am33xx_eqep_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
};
|
|
|
|
/* ehrpwm2 */
|
|
struct omap_hwmod am33xx_ehrpwm2_hwmod = {
|
|
.name = "ehrpwm2",
|
|
.class = &am33xx_ehrpwm_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
};
|
|
|
|
/*
|
|
* 'gpio' class: for gpio 0,1,2,3
|
|
*/
|
|
static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0114,
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
struct omap_hwmod_class am33xx_gpio_hwmod_class = {
|
|
.name = "gpio",
|
|
.sysc = &am33xx_gpio_sysc,
|
|
.rev = 2,
|
|
};
|
|
|
|
struct omap_gpio_dev_attr gpio_dev_attr = {
|
|
.bank_width = 32,
|
|
.dbck_flag = true,
|
|
};
|
|
|
|
/* gpio1 */
|
|
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
|
|
{ .role = "dbclk", .clk = "gpio1_dbclk" },
|
|
};
|
|
|
|
struct omap_hwmod am33xx_gpio1_hwmod = {
|
|
.name = "gpio2",
|
|
.class = &am33xx_gpio_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.opt_clks = gpio1_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
|
|
.dev_attr = &gpio_dev_attr,
|
|
};
|
|
|
|
/* gpio2 */
|
|
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
|
|
{ .role = "dbclk", .clk = "gpio2_dbclk" },
|
|
};
|
|
|
|
struct omap_hwmod am33xx_gpio2_hwmod = {
|
|
.name = "gpio3",
|
|
.class = &am33xx_gpio_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.opt_clks = gpio2_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
|
|
.dev_attr = &gpio_dev_attr,
|
|
};
|
|
|
|
/* gpio3 */
|
|
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
|
|
{ .role = "dbclk", .clk = "gpio3_dbclk" },
|
|
};
|
|
|
|
struct omap_hwmod am33xx_gpio3_hwmod = {
|
|
.name = "gpio4",
|
|
.class = &am33xx_gpio_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.opt_clks = gpio3_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
|
|
.dev_attr = &gpio_dev_attr,
|
|
};
|
|
|
|
/* gpmc */
|
|
static struct omap_hwmod_class_sysconfig gpmc_sysc = {
|
|
.rev_offs = 0x0,
|
|
.sysc_offs = 0x10,
|
|
.syss_offs = 0x14,
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
|
|
.name = "gpmc",
|
|
.sysc = &gpmc_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_gpmc_hwmod = {
|
|
.name = "gpmc",
|
|
.class = &am33xx_gpmc_hwmod_class,
|
|
.clkdm_name = "l3s_clkdm",
|
|
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
|
|
.main_clk = "l3s_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* 'i2c' class */
|
|
static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0090,
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class i2c_class = {
|
|
.name = "i2c",
|
|
.sysc = &am33xx_i2c_sysc,
|
|
.rev = OMAP_I2C_IP_VERSION_2,
|
|
.reset = &omap_i2c_reset,
|
|
};
|
|
|
|
static struct omap_i2c_dev_attr i2c_dev_attr = {
|
|
.flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
|
|
};
|
|
|
|
/* i2c1 */
|
|
struct omap_hwmod am33xx_i2c1_hwmod = {
|
|
.name = "i2c1",
|
|
.class = &i2c_class,
|
|
.clkdm_name = "l4_wkup_clkdm",
|
|
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
|
|
.main_clk = "dpll_per_m2_div4_wkupdm_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.dev_attr = &i2c_dev_attr,
|
|
};
|
|
|
|
/* i2c1 */
|
|
struct omap_hwmod am33xx_i2c2_hwmod = {
|
|
.name = "i2c2",
|
|
.class = &i2c_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
|
|
.main_clk = "dpll_per_m2_div4_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.dev_attr = &i2c_dev_attr,
|
|
};
|
|
|
|
/* i2c3 */
|
|
struct omap_hwmod am33xx_i2c3_hwmod = {
|
|
.name = "i2c3",
|
|
.class = &i2c_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
|
|
.main_clk = "dpll_per_m2_div4_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.dev_attr = &i2c_dev_attr,
|
|
};
|
|
|
|
/*
|
|
* 'mailbox' class
|
|
* mailbox module allowing communication between the on-chip processors using a
|
|
* queued mailbox-interrupt mechanism.
|
|
*/
|
|
static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
|
|
.name = "mailbox",
|
|
.sysc = &am33xx_mailbox_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_mailbox_hwmod = {
|
|
.name = "mailbox",
|
|
.class = &am33xx_mailbox_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'mcasp' class
|
|
*/
|
|
static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
|
|
.rev_offs = 0x0,
|
|
.sysc_offs = 0x4,
|
|
.sysc_flags = SYSC_HAS_SIDLEMODE,
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type3,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
|
|
.name = "mcasp",
|
|
.sysc = &am33xx_mcasp_sysc,
|
|
};
|
|
|
|
/* mcasp0 */
|
|
struct omap_hwmod am33xx_mcasp0_hwmod = {
|
|
.name = "mcasp0",
|
|
.class = &am33xx_mcasp_hwmod_class,
|
|
.clkdm_name = "l3s_clkdm",
|
|
.main_clk = "mcasp0_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* mcasp1 */
|
|
struct omap_hwmod am33xx_mcasp1_hwmod = {
|
|
.name = "mcasp1",
|
|
.class = &am33xx_mcasp_hwmod_class,
|
|
.clkdm_name = "l3s_clkdm",
|
|
.main_clk = "mcasp1_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* 'mmc' class */
|
|
static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
|
|
.rev_offs = 0x1fc,
|
|
.sysc_offs = 0x10,
|
|
.syss_offs = 0x14,
|
|
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
|
|
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
|
|
.name = "mmc",
|
|
.sysc = &am33xx_mmc_sysc,
|
|
};
|
|
|
|
/* mmc0 */
|
|
static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
|
|
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_mmc0_hwmod = {
|
|
.name = "mmc1",
|
|
.class = &am33xx_mmc_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "mmc_clk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.dev_attr = &am33xx_mmc0_dev_attr,
|
|
};
|
|
|
|
/* mmc1 */
|
|
static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
|
|
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_mmc1_hwmod = {
|
|
.name = "mmc2",
|
|
.class = &am33xx_mmc_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "mmc_clk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.dev_attr = &am33xx_mmc1_dev_attr,
|
|
};
|
|
|
|
/* mmc2 */
|
|
static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
|
|
.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
|
|
};
|
|
struct omap_hwmod am33xx_mmc2_hwmod = {
|
|
.name = "mmc3",
|
|
.class = &am33xx_mmc_hwmod_class,
|
|
.clkdm_name = "l3s_clkdm",
|
|
.main_clk = "mmc_clk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.dev_attr = &am33xx_mmc2_dev_attr,
|
|
};
|
|
|
|
/*
|
|
* 'rtc' class
|
|
* rtc subsystem
|
|
*/
|
|
static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
|
|
.rev_offs = 0x0074,
|
|
.sysc_offs = 0x0078,
|
|
.sysc_flags = SYSC_HAS_SIDLEMODE,
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO |
|
|
SIDLE_SMART | SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type3,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
|
|
.name = "rtc",
|
|
.sysc = &am33xx_rtc_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_rtc_hwmod = {
|
|
.name = "rtc",
|
|
.class = &am33xx_rtc_hwmod_class,
|
|
.clkdm_name = "l4_rtc_clkdm",
|
|
.main_clk = "clk_32768_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* 'spi' class */
|
|
static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0110,
|
|
.syss_offs = 0x0114,
|
|
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
|
|
SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
struct omap_hwmod_class am33xx_spi_hwmod_class = {
|
|
.name = "mcspi",
|
|
.sysc = &am33xx_mcspi_sysc,
|
|
.rev = OMAP4_MCSPI_REV,
|
|
};
|
|
|
|
/* spi0 */
|
|
struct omap2_mcspi_dev_attr mcspi_attrib = {
|
|
.num_chipselect = 2,
|
|
};
|
|
struct omap_hwmod am33xx_spi0_hwmod = {
|
|
.name = "spi0",
|
|
.class = &am33xx_spi_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "dpll_per_m2_div4_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.dev_attr = &mcspi_attrib,
|
|
};
|
|
|
|
/* spi1 */
|
|
struct omap_hwmod am33xx_spi1_hwmod = {
|
|
.name = "spi1",
|
|
.class = &am33xx_spi_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "dpll_per_m2_div4_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.dev_attr = &mcspi_attrib,
|
|
};
|
|
|
|
/*
|
|
* 'spinlock' class
|
|
* spinlock provides hardware assistance for synchronizing the
|
|
* processes running on multiple processors
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
|
|
.name = "spinlock",
|
|
.sysc = &am33xx_spinlock_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_spinlock_hwmod = {
|
|
.name = "spinlock",
|
|
.class = &am33xx_spinlock_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "l4ls_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* 'timer 2-7' class */
|
|
static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
struct omap_hwmod_class am33xx_timer_hwmod_class = {
|
|
.name = "timer",
|
|
.sysc = &am33xx_timer_sysc,
|
|
};
|
|
|
|
/* timer1 1ms */
|
|
static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
|
|
SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
|
|
.name = "timer",
|
|
.sysc = &am33xx_timer1ms_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer1_hwmod = {
|
|
.name = "timer1",
|
|
.class = &am33xx_timer1ms_hwmod_class,
|
|
.clkdm_name = "l4_wkup_clkdm",
|
|
.main_clk = "timer1_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer2_hwmod = {
|
|
.name = "timer2",
|
|
.class = &am33xx_timer_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "timer2_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer3_hwmod = {
|
|
.name = "timer3",
|
|
.class = &am33xx_timer_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "timer3_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer4_hwmod = {
|
|
.name = "timer4",
|
|
.class = &am33xx_timer_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "timer4_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer5_hwmod = {
|
|
.name = "timer5",
|
|
.class = &am33xx_timer_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "timer5_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer6_hwmod = {
|
|
.name = "timer6",
|
|
.class = &am33xx_timer_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "timer6_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_timer7_hwmod = {
|
|
.name = "timer7",
|
|
.class = &am33xx_timer_hwmod_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.main_clk = "timer7_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* tpcc */
|
|
static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
|
|
.name = "tpcc",
|
|
};
|
|
|
|
struct omap_hwmod am33xx_tpcc_hwmod = {
|
|
.name = "tpcc",
|
|
.class = &am33xx_tpcc_hwmod_class,
|
|
.clkdm_name = "l3_clkdm",
|
|
.main_clk = "l3_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
|
|
.rev_offs = 0x0,
|
|
.sysc_offs = 0x10,
|
|
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
SYSC_HAS_MIDLEMODE),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
/* 'tptc' class */
|
|
static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
|
|
.name = "tptc",
|
|
.sysc = &am33xx_tptc_sysc,
|
|
};
|
|
|
|
/* tptc0 */
|
|
struct omap_hwmod am33xx_tptc0_hwmod = {
|
|
.name = "tptc0",
|
|
.class = &am33xx_tptc_hwmod_class,
|
|
.clkdm_name = "l3_clkdm",
|
|
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
|
.main_clk = "l3_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* tptc1 */
|
|
struct omap_hwmod am33xx_tptc1_hwmod = {
|
|
.name = "tptc1",
|
|
.class = &am33xx_tptc_hwmod_class,
|
|
.clkdm_name = "l3_clkdm",
|
|
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
|
|
.main_clk = "l3_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* tptc2 */
|
|
struct omap_hwmod am33xx_tptc2_hwmod = {
|
|
.name = "tptc2",
|
|
.class = &am33xx_tptc_hwmod_class,
|
|
.clkdm_name = "l3_clkdm",
|
|
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
|
|
.main_clk = "l3_gclk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* 'uart' class */
|
|
static struct omap_hwmod_class_sysconfig uart_sysc = {
|
|
.rev_offs = 0x50,
|
|
.sysc_offs = 0x54,
|
|
.syss_offs = 0x58,
|
|
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
|
|
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class uart_class = {
|
|
.name = "uart",
|
|
.sysc = &uart_sysc,
|
|
};
|
|
|
|
struct omap_hwmod am33xx_uart1_hwmod = {
|
|
.name = "uart1",
|
|
.class = &uart_class,
|
|
.clkdm_name = "l4_wkup_clkdm",
|
|
.flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
|
|
.main_clk = "dpll_per_m2_div4_wkupdm_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_uart2_hwmod = {
|
|
.name = "uart2",
|
|
.class = &uart_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_SWSUP_SIDLE_ACT,
|
|
.main_clk = "dpll_per_m2_div4_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* uart3 */
|
|
struct omap_hwmod am33xx_uart3_hwmod = {
|
|
.name = "uart3",
|
|
.class = &uart_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_SWSUP_SIDLE_ACT,
|
|
.main_clk = "dpll_per_m2_div4_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_uart4_hwmod = {
|
|
.name = "uart4",
|
|
.class = &uart_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_SWSUP_SIDLE_ACT,
|
|
.main_clk = "dpll_per_m2_div4_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_uart5_hwmod = {
|
|
.name = "uart5",
|
|
.class = &uart_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_SWSUP_SIDLE_ACT,
|
|
.main_clk = "dpll_per_m2_div4_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
struct omap_hwmod am33xx_uart6_hwmod = {
|
|
.name = "uart6",
|
|
.class = &uart_class,
|
|
.clkdm_name = "l4ls_clkdm",
|
|
.flags = HWMOD_SWSUP_SIDLE_ACT,
|
|
.main_clk = "dpll_per_m2_div4_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* 'wd_timer' class */
|
|
static struct omap_hwmod_class_sysconfig wdt_sysc = {
|
|
.rev_offs = 0x0,
|
|
.sysc_offs = 0x10,
|
|
.syss_offs = 0x14,
|
|
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
|
|
.name = "wd_timer",
|
|
.sysc = &wdt_sysc,
|
|
.pre_shutdown = &omap2_wd_timer_disable,
|
|
};
|
|
|
|
/*
|
|
* XXX: device.c file uses hardcoded name for watchdog timer
|
|
* driver "wd_timer2, so we are also using same name as of now...
|
|
*/
|
|
struct omap_hwmod am33xx_wd_timer1_hwmod = {
|
|
.name = "wd_timer2",
|
|
.class = &am33xx_wd_timer_hwmod_class,
|
|
.clkdm_name = "l4_wkup_clkdm",
|
|
.flags = HWMOD_SWSUP_SIDLE,
|
|
.main_clk = "wdt1_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
static void omap_hwmod_am33xx_clkctrl(void)
|
|
{
|
|
CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_smartreflex0_hwmod,
|
|
AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_smartreflex1_hwmod,
|
|
AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
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}
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static void omap_hwmod_am33xx_rst(void)
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{
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RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
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RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
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RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
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}
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void omap_hwmod_am33xx_reg(void)
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{
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omap_hwmod_am33xx_clkctrl();
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omap_hwmod_am33xx_rst();
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}
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static void omap_hwmod_am43xx_clkctrl(void)
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{
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CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
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CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
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|
CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
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|
CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
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|
CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
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|
CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
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|
CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
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|
CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
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|
CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
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|
CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_smartreflex0_hwmod,
|
|
AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_smartreflex1_hwmod,
|
|
AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
|
|
CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
|
|
}
|
|
|
|
static void omap_hwmod_am43xx_rst(void)
|
|
{
|
|
RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
|
|
RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
|
|
RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
|
|
}
|
|
|
|
void omap_hwmod_am43xx_reg(void)
|
|
{
|
|
omap_hwmod_am43xx_clkctrl();
|
|
omap_hwmod_am43xx_rst();
|
|
}
|