forked from Minki/linux
825f4e0271
A quite large set of SoC updates this cycle. In no particular order:
- Multi-cluster power management for Samsung Exynos, adding support for
big.LITTLE CPU switching on EXYNOS5
- SMP support for Marvell Armada 375 and 38x
- SMP rework on Allwinner A31
- Xilinx Zynq support for SOC_BUS, big endian
- Marvell orion5x platform cleanup, modernizing the implementation and
moving to DT.
- _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so
that their platform can be enabled in the same kernel binary as most
of the other v7 platforms in the tree. \o/ The work isn't quite complete,
there's some driver fixes still needed, but the basics now work.
New SoC support added:
- Freescale i.MX6SX
- LSI Axxia AXM55xx SoCs
- Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800
- STi STIH407
Plus a large set of various smaller updates for different platforms. I'm
probably missing some important one here.
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Merge tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next
Pull part one of ARM SoC updates from Olof Johansson:
"A quite large set of SoC updates this cycle. In no particular order:
- Multi-cluster power management for Samsung Exynos, adding support
for big.LITTLE CPU switching on EXYNOS5
- SMP support for Marvell Armada 375 and 38x
- SMP rework on Allwinner A31
- Xilinx Zynq support for SOC_BUS, big endian
- Marvell orion5x platform cleanup, modernizing the implementation
and moving to DT.
- _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so
that their platform can be enabled in the same kernel binary as
most of the other v7 platforms in the tree. \o/
The work isn't quite complete, there's some driver fixes still
needed, but the basics now work.
New SoC support added:
- Freescale i.MX6SX
- LSI Axxia AXM55xx SoCs
- Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800
- STi STIH407
plus a large set of various smaller updates for different platforms.
I'm probably missing some important one here"
* tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (281 commits)
ARM: exynos: don't run exynos4 l2x0 setup on other platforms
ARM: exynos: Fix "allmodconfig" build errors in mcpm and hotplug
ARM: EXYNOS: mcpm rename the power_down_finish
ARM: EXYNOS: Enable mcpm for dual-cluster exynos5800 SoC
ARM: EXYNOS: Enable multi-platform build support
ARM: EXYNOS: Consolidate Kconfig entries
ARM: EXYNOS: Add support for EXYNOS5410 SoC
ARM: EXYNOS: Support secondary CPU boot of Exynos3250
ARM: EXYNOS: Add Exynos3250 SoC ID
ARM: EXYNOS: Add 5800 SoC support
ARM: EXYNOS: initial board support for exynos5260 SoC
clk: exynos5410: register clocks using common clock framework
ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084
ARM: sunxi: allow building without reset controller
Documentation: devicetree: arm: sort enable-method entries
ARM: rockchip: convert smp bringup to CPU_METHOD_OF_DECLARE
clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks
ARM: dts: axxia: Add reset controller
power: reset: Add Axxia system reset driver
ARM: axxia: Adding defconfig for AXM55xx
...
777 lines
18 KiB
Plaintext
777 lines
18 KiB
Plaintext
/*
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* SAMSUNG EXYNOS5420 SoC device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
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* EXYNOS5420 based board files can include this file and provide
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* values for board specfic bindings.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/exynos5420.h>
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#include "exynos5.dtsi"
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#include "exynos5420-pinctrl.dtsi"
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#include <dt-bindings/clock/exynos-audss-clk.h>
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/ {
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compatible = "samsung,exynos5420", "samsung,exynos5";
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aliases {
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mshc0 = &mmc_0;
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mshc1 = &mmc_1;
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mshc2 = &mmc_2;
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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pinctrl3 = &pinctrl_3;
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pinctrl4 = &pinctrl_4;
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i2c0 = &i2c_0;
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i2c1 = &i2c_1;
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i2c2 = &i2c_2;
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i2c3 = &i2c_3;
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i2c4 = &hsi2c_4;
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i2c5 = &hsi2c_5;
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i2c6 = &hsi2c_6;
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i2c7 = &hsi2c_7;
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i2c8 = &hsi2c_8;
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i2c9 = &hsi2c_9;
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i2c10 = &hsi2c_10;
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gsc0 = &gsc_0;
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gsc1 = &gsc_1;
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spi0 = &spi_0;
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spi1 = &spi_1;
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spi2 = &spi_2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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};
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cci@10d20000 {
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compatible = "arm,cci-400";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10d20000 0x1000>;
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ranges = <0x0 0x10d20000 0x6000>;
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cci_control0: slave-if@4000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x4000 0x1000>;
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};
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cci_control1: slave-if@5000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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};
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};
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sysram@02020000 {
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compatible = "mmio-sram";
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reg = <0x02020000 0x54000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x02020000 0x54000>;
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smp-sysram@0 {
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compatible = "samsung,exynos4210-sysram";
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reg = <0x0 0x1000>;
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};
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smp-sysram@53000 {
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compatible = "samsung,exynos4210-sysram-ns";
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reg = <0x53000 0x1000>;
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};
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};
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clock: clock-controller@10010000 {
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compatible = "samsung,exynos5420-clock";
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reg = <0x10010000 0x30000>;
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#clock-cells = <1>;
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};
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clock_audss: audss-clock-controller@3810000 {
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compatible = "samsung,exynos5420-audss-clock";
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reg = <0x03810000 0x0C>;
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#clock-cells = <1>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
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<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
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clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
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};
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mfc: codec@11000000 {
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compatible = "samsung,mfc-v7";
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reg = <0x11000000 0x10000>;
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interrupts = <0 96 0>;
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clocks = <&clock CLK_MFC>;
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clock-names = "mfc";
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};
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mmc_0: mmc@12200000 {
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compatible = "samsung,exynos5420-dw-mshc-smu";
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interrupts = <0 75 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12200000 0x2000>;
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clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mmc_1: mmc@12210000 {
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compatible = "samsung,exynos5420-dw-mshc-smu";
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interrupts = <0 76 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12210000 0x2000>;
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clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mmc_2: mmc@12220000 {
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compatible = "samsung,exynos5420-dw-mshc";
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interrupts = <0 77 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12220000 0x1000>;
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clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mct: mct@101C0000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x101C0000 0x800>;
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interrupt-controller;
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#interrups-cells = <1>;
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interrupt-parent = <&mct_map>;
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interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
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<8>, <9>, <10>, <11>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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clock-names = "fin_pll", "mct";
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mct_map: mct-map {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <0 &combiner 23 3>,
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<1 &combiner 23 4>,
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<2 &combiner 25 2>,
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<3 &combiner 25 3>,
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<4 &gic 0 120 0>,
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<5 &gic 0 121 0>,
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<6 &gic 0 122 0>,
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<7 &gic 0 123 0>,
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<8 &gic 0 128 0>,
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<9 &gic 0 129 0>,
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<10 &gic 0 130 0>,
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<11 &gic 0 131 0>;
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};
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};
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gsc_pd: power-domain@10044000 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044000 0x20>;
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};
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isp_pd: power-domain@10044020 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044020 0x20>;
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};
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mfc_pd: power-domain@10044060 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044060 0x20>;
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};
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disp_pd: power-domain@100440C0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x100440C0 0x20>;
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};
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msc_pd: power-domain@10044120 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044120 0x20>;
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};
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pinctrl_0: pinctrl@13400000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x13400000 0x1000>;
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interrupts = <0 45 0>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <0 32 0>;
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};
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};
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pinctrl_1: pinctrl@13410000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x13410000 0x1000>;
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interrupts = <0 78 0>;
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};
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pinctrl_2: pinctrl@14000000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x14000000 0x1000>;
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interrupts = <0 46 0>;
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};
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pinctrl_3: pinctrl@14010000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x14010000 0x1000>;
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interrupts = <0 50 0>;
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};
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pinctrl_4: pinctrl@03860000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x03860000 0x1000>;
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interrupts = <0 47 0>;
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};
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rtc: rtc@101E0000 {
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clocks = <&clock CLK_RTC>;
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clock-names = "rtc";
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status = "disabled";
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};
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,amba-bus";
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interrupt-parent = <&gic>;
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ranges;
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adma: adma@03880000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x03880000 0x1000>;
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interrupts = <0 110 0>;
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clocks = <&clock_audss EXYNOS_ADMA>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <6>;
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#dma-requests = <16>;
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};
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pdma0: pdma@121A0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x121A0000 0x1000>;
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interrupts = <0 34 0>;
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clocks = <&clock CLK_PDMA0>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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pdma1: pdma@121B0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x121B0000 0x1000>;
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interrupts = <0 35 0>;
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clocks = <&clock CLK_PDMA1>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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mdma0: mdma@10800000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x10800000 0x1000>;
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interrupts = <0 33 0>;
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clocks = <&clock CLK_MDMA0>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <1>;
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};
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mdma1: mdma@11C10000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x11C10000 0x1000>;
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interrupts = <0 124 0>;
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clocks = <&clock CLK_MDMA1>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <1>;
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/*
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* MDMA1 can support both secure and non-secure
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* AXI transactions. When this is enabled in the kernel
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* for boards that run in secure mode, we are getting
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* imprecise external aborts causing the kernel to oops.
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*/
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status = "disabled";
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};
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};
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i2s0: i2s@03830000 {
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compatible = "samsung,exynos5420-i2s";
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reg = <0x03830000 0x100>;
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dmas = <&adma 0
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&adma 2
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&adma 1>;
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dma-names = "tx", "rx", "tx-sec";
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clocks = <&clock_audss EXYNOS_I2S_BUS>,
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<&clock_audss EXYNOS_I2S_BUS>,
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<&clock_audss EXYNOS_SCLK_I2S>;
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clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
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samsung,idma-addr = <0x03000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_bus>;
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status = "disabled";
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};
|
|
|
|
i2s1: i2s@12D60000 {
|
|
compatible = "samsung,exynos5420-i2s";
|
|
reg = <0x12D60000 0x100>;
|
|
dmas = <&pdma1 12
|
|
&pdma1 11>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
|
|
clock-names = "iis", "i2s_opclk0";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s1_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s2: i2s@12D70000 {
|
|
compatible = "samsung,exynos5420-i2s";
|
|
reg = <0x12D70000 0x100>;
|
|
dmas = <&pdma0 12
|
|
&pdma0 11>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
|
|
clock-names = "iis", "i2s_opclk0";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s2_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_0: spi@12d20000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x12d20000 0x100>;
|
|
interrupts = <0 68 0>;
|
|
dmas = <&pdma0 5
|
|
&pdma0 4>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_bus>;
|
|
clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_1: spi@12d30000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x12d30000 0x100>;
|
|
interrupts = <0 69 0>;
|
|
dmas = <&pdma1 5
|
|
&pdma1 4>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_bus>;
|
|
clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_2: spi@12d40000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x12d40000 0x100>;
|
|
interrupts = <0 70 0>;
|
|
dmas = <&pdma0 7
|
|
&pdma0 6>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi2_bus>;
|
|
clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart_0: serial@12C00000 {
|
|
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|
|
|
|
uart_1: serial@12C10000 {
|
|
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|
|
|
|
uart_2: serial@12C20000 {
|
|
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|
|
|
|
uart_3: serial@12C30000 {
|
|
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|
|
|
|
pwm: pwm@12dd0000 {
|
|
compatible = "samsung,exynos4210-pwm";
|
|
reg = <0x12dd0000 0x100>;
|
|
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&clock CLK_PWM>;
|
|
clock-names = "timers";
|
|
};
|
|
|
|
dp_phy: video-phy@10040728 {
|
|
compatible = "samsung,exynos5250-dp-video-phy";
|
|
reg = <0x10040728 4>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
dp: dp-controller@145B0000 {
|
|
clocks = <&clock CLK_DP1>;
|
|
clock-names = "dp";
|
|
phys = <&dp_phy>;
|
|
phy-names = "dp";
|
|
};
|
|
|
|
fimd: fimd@14400000 {
|
|
samsung,power-domain = <&disp_pd>;
|
|
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
|
|
clock-names = "sclk_fimd", "fimd";
|
|
};
|
|
|
|
adc: adc@12D10000 {
|
|
compatible = "samsung,exynos-adc-v2";
|
|
reg = <0x12D10000 0x100>, <0x10040720 0x4>;
|
|
interrupts = <0 106 0>;
|
|
clocks = <&clock CLK_TSADC>;
|
|
clock-names = "adc";
|
|
#io-channel-cells = <1>;
|
|
io-channel-ranges;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_0: i2c@12C60000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C60000 0x100>;
|
|
interrupts = <0 56 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock CLK_I2C0>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_1: i2c@12C70000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C70000 0x100>;
|
|
interrupts = <0 57 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock CLK_I2C1>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_2: i2c@12C80000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C80000 0x100>;
|
|
interrupts = <0 58 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock CLK_I2C2>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_3: i2c@12C90000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C90000 0x100>;
|
|
interrupts = <0 59 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock CLK_I2C3>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_4: i2c@12CA0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CA0000 0x1000>;
|
|
interrupts = <0 60 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_hs_bus>;
|
|
clocks = <&clock CLK_USI0>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_5: i2c@12CB0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CB0000 0x1000>;
|
|
interrupts = <0 61 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5_hs_bus>;
|
|
clocks = <&clock CLK_USI1>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_6: i2c@12CC0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CC0000 0x1000>;
|
|
interrupts = <0 62 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6_hs_bus>;
|
|
clocks = <&clock CLK_USI2>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_7: i2c@12CD0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CD0000 0x1000>;
|
|
interrupts = <0 63 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c7_hs_bus>;
|
|
clocks = <&clock CLK_USI3>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_8: i2c@12E00000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12E00000 0x1000>;
|
|
interrupts = <0 87 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c8_hs_bus>;
|
|
clocks = <&clock CLK_USI4>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_9: i2c@12E10000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12E10000 0x1000>;
|
|
interrupts = <0 88 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c9_hs_bus>;
|
|
clocks = <&clock CLK_USI5>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_10: i2c@12E20000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12E20000 0x1000>;
|
|
interrupts = <0 203 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c10_hs_bus>;
|
|
clocks = <&clock CLK_USI6>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hdmi: hdmi@14530000 {
|
|
compatible = "samsung,exynos4212-hdmi";
|
|
reg = <0x14530000 0x70000>;
|
|
interrupts = <0 95 0>;
|
|
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
|
|
<&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
|
|
<&clock CLK_MOUT_HDMI>;
|
|
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
|
|
"sclk_hdmiphy", "mout_hdmi";
|
|
status = "disabled";
|
|
};
|
|
|
|
mixer: mixer@14450000 {
|
|
compatible = "samsung,exynos5420-mixer";
|
|
reg = <0x14450000 0x10000>;
|
|
interrupts = <0 94 0>;
|
|
clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
|
|
clock-names = "mixer", "sclk_hdmi";
|
|
};
|
|
|
|
gsc_0: video-scaler@13e00000 {
|
|
compatible = "samsung,exynos5-gsc";
|
|
reg = <0x13e00000 0x1000>;
|
|
interrupts = <0 85 0>;
|
|
clocks = <&clock CLK_GSCL0>;
|
|
clock-names = "gscl";
|
|
samsung,power-domain = <&gsc_pd>;
|
|
};
|
|
|
|
gsc_1: video-scaler@13e10000 {
|
|
compatible = "samsung,exynos5-gsc";
|
|
reg = <0x13e10000 0x1000>;
|
|
interrupts = <0 86 0>;
|
|
clocks = <&clock CLK_GSCL1>;
|
|
clock-names = "gscl";
|
|
samsung,power-domain = <&gsc_pd>;
|
|
};
|
|
|
|
pmu_system_controller: system-controller@10040000 {
|
|
compatible = "samsung,exynos5420-pmu", "syscon";
|
|
reg = <0x10040000 0x5000>;
|
|
};
|
|
|
|
tmu_cpu0: tmu@10060000 {
|
|
compatible = "samsung,exynos5420-tmu";
|
|
reg = <0x10060000 0x100>;
|
|
interrupts = <0 65 0>;
|
|
clocks = <&clock CLK_TMU>;
|
|
clock-names = "tmu_apbif";
|
|
};
|
|
|
|
tmu_cpu1: tmu@10064000 {
|
|
compatible = "samsung,exynos5420-tmu";
|
|
reg = <0x10064000 0x100>;
|
|
interrupts = <0 183 0>;
|
|
clocks = <&clock CLK_TMU>;
|
|
clock-names = "tmu_apbif";
|
|
};
|
|
|
|
tmu_cpu2: tmu@10068000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
|
|
interrupts = <0 184 0>;
|
|
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
};
|
|
|
|
tmu_cpu3: tmu@1006c000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
|
|
interrupts = <0 185 0>;
|
|
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
};
|
|
|
|
tmu_gpu: tmu@100a0000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x100a0000 0x100>, <0x10068000 0x4>;
|
|
interrupts = <0 215 0>;
|
|
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
};
|
|
|
|
watchdog: watchdog@101D0000 {
|
|
compatible = "samsung,exynos5420-wdt";
|
|
reg = <0x101D0000 0x100>;
|
|
interrupts = <0 42 0>;
|
|
clocks = <&clock CLK_WDT>;
|
|
clock-names = "watchdog";
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
};
|
|
|
|
sss: sss@10830000 {
|
|
compatible = "samsung,exynos4210-secss";
|
|
reg = <0x10830000 0x10000>;
|
|
interrupts = <0 112 0>;
|
|
clocks = <&clock 471>;
|
|
clock-names = "secss";
|
|
};
|
|
};
|