c09d6a04d1
On CPUs which support the LSE atomic instructions introduced in ARMv8.1, it makes sense to use them in preference to ll/sc sequences. This patch introduces runtime patching of atomic_t and atomic64_t routines so that the call-site for the out-of-line ll/sc sequences is patched with an LSE atomic instruction when we detect that the CPU supports it. If binutils is not recent enough to assemble the LSE instructions, then the ll/sc sequences are inlined as though CONFIG_ARM64_LSE_ATOMICS=n. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
35 lines
883 B
C
35 lines
883 B
C
#ifndef __ASM_LSE_H
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#define __ASM_LSE_H
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#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
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#include <linux/stringify.h>
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#include <asm/alternative.h>
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#include <asm/cpufeature.h>
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__asm__(".arch_extension lse");
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/* Move the ll/sc atomics out-of-line */
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#define __LL_SC_INLINE
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#define __LL_SC_PREFIX(x) __ll_sc_##x
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#define __LL_SC_EXPORT(x) EXPORT_SYMBOL(__LL_SC_PREFIX(x))
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/* Macro for constructing calls to out-of-line ll/sc atomics */
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#define __LL_SC_CALL(op) "bl\t" __stringify(__LL_SC_PREFIX(op)) "\n"
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/* In-line patching at runtime */
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#define ARM64_LSE_ATOMIC_INSN(llsc, lse) \
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ALTERNATIVE(llsc, lse, ARM64_CPU_FEAT_LSE_ATOMICS)
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#else
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#define __LL_SC_INLINE static inline
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#define __LL_SC_PREFIX(x) x
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#define __LL_SC_EXPORT(x)
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#define ARM64_LSE_ATOMIC_INSN(llsc, lse) llsc
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#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
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#endif /* __ASM_LSE_H */
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