forked from Minki/linux
81490fcdf4
Ethernet hangs off OTG Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
122 lines
3.3 KiB
C
122 lines
3.3 KiB
C
/*
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* Copyright (C) 2010 Linaro Limited
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*
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* based on code from the following
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* Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
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* Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/fsl_devices.h>
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#include <mach/common.h>
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#include <mach/hardware.h>
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#include <mach/iomux-mx51.h>
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#include <mach/i2c.h>
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#include <mach/mxc_ehci.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include "devices-imx51.h"
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#include "devices.h"
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#define MX51_USB_PLL_DIV_24_MHZ 0x01
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static struct pad_desc mx51efikamx_pads[] = {
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/* UART1 */
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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MX51_PAD_UART1_RTS__UART1_RTS,
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MX51_PAD_UART1_CTS__UART1_CTS,
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};
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/* Serial ports */
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#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
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static const struct imxuart_platform_data uart_pdata = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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static inline void mxc_init_imx_uart(void)
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{
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imx51_add_imx_uart(0, &uart_pdata);
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imx51_add_imx_uart(1, &uart_pdata);
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imx51_add_imx_uart(2, &uart_pdata);
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}
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#else /* !SERIAL_IMX */
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static inline void mxc_init_imx_uart(void)
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{
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}
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#endif /* SERIAL_IMX */
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/* This function is board specific as the bit mask for the plldiv will also
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* be different for other Freescale SoCs, thus a common bitmask is not
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* possible and cannot get place in /plat-mxc/ehci.c.
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*/
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static int initialize_otg_port(struct platform_device *pdev)
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{
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u32 v;
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void __iomem *usb_base;
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void __iomem *usbother_base;
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usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
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usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
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/* Set the PHY clock to 19.2MHz */
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v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
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v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
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v |= MX51_USB_PLL_DIV_24_MHZ;
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__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
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iounmap(usb_base);
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return 0;
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}
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static struct mxc_usbh_platform_data dr_utmi_config = {
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.init = initialize_otg_port,
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.portsc = MXC_EHCI_UTMI_16BIT,
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.flags = MXC_EHCI_INTERNAL_PHY,
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};
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static void __init mxc_board_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
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ARRAY_SIZE(mx51efikamx_pads));
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mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
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mxc_init_imx_uart();
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}
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static void __init mx51_efikamx_timer_init(void)
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{
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mx51_clocks_init(32768, 24000000, 22579200, 24576000);
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}
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static struct sys_timer mxc_timer = {
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.init = mx51_efikamx_timer_init,
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};
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MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
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/* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
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.phys_io = MX51_AIPS1_BASE_ADDR,
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.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
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.boot_params = MX51_PHYS_OFFSET + 0x100,
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.map_io = mx51_map_io,
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.init_irq = mx51_init_irq,
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.init_machine = mxc_board_init,
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.timer = &mxc_timer,
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MACHINE_END
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