cb80705549
Limit pre-skl plane stride to below 4k or 8k pixels (depending on the platform). We do this in order guarantee that TILEOFF/OFFSET.x does not get too big. Currently this is not a problem as we align SURF to 4k, and so TILEOFF/OFFSET only have to deal with a single tile's worth of pixels. But for async flips we're going to have to bump SURF alignment to 256k, and thus we can no longer guarantee TILEOFF/OFFSET.x will stay within acceptable bounds. We can avoid this by borrowing a trick from the skl+ code and limit the max plane stride to whatever value we can fit into TILEOFF/OFFSET.x. The slight downside is that we may end up doing GTT remapping in a few more cases where previously we did not have to. But since that will only happen with huge buffers I'm not really concerned about it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-3-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
25 lines
548 B
C
25 lines
548 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#ifndef _I9XX_PLANE_H_
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#define _I9XX_PLANE_H_
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#include <linux/types.h>
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enum pipe;
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struct drm_i915_private;
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struct intel_plane;
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struct intel_plane_state;
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unsigned int i965_plane_max_stride(struct intel_plane *plane,
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u32 pixel_format, u64 modifier,
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unsigned int rotation);
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int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
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struct intel_plane *
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intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe);
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#endif
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