Dillon Varone beb6b2f97e drm/amd/display: Remove MPC gamut remap logic for DCN30 ... [Why?] Should only reroute gamut remap to mpc unless 3D LUT is not used and all planes are using the same src->dest. [How?] Remove DCN30 specific logic for rerouting gamut remap to mpc. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1513 Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org		2021-03-18 00:05:22 -04:00
..
dcn20_dccg.c	drm/amd/display: DPP DTO isn't update properly.	2020-03-19 00:03:04 -04:00
dcn20_dccg.h	drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)	2020-11-04 17:11:37 -05:00
dcn20_dpp_cm.c	drm/amd/display: Indirect reg read macro with shift and mask	2020-01-16 14:13:53 -05:00
dcn20_dpp.c	drm/amd/display: correct alpha_en programming for new pixel format	2020-07-01 01:59:19 -04:00
dcn20_dpp.h	drm/amd/display: Add DSCL memory low power support	2020-12-01 16:03:40 -05:00
dcn20_dsc.c	drm/amd/display: Rename bytes_pp to the correct bits_pp	2020-07-27 16:23:21 -04:00
dcn20_dsc.h	drm/amd/display: Add DSC_DBG_EN shift/mask for dcn3	2020-08-17 14:09:27 -04:00
dcn20_dwb_scl.c	drm/amd/display: Remove set but not used variables 'h_ratio_chroma', 'v_ratio_chroma'	2019-10-07 15:10:43 -05:00
dcn20_dwb.c
dcn20_dwb.h
dcn20_hubbub.c	drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)	2020-11-04 17:11:37 -05:00
dcn20_hubbub.h	drm/amd/display: correct rn NUM_VMID	2020-05-21 12:48:43 -04:00
dcn20_hubp.c	drm/amd/display: Enable pflip interrupt upon pipe enable	2021-03-10 16:14:36 -05:00
dcn20_hubp.h	drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)	2020-11-04 17:11:37 -05:00
dcn20_hwseq.c	drm/amd/display: Remove MPC gamut remap logic for DCN30	2021-03-18 00:05:22 -04:00
dcn20_hwseq.h	drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2	2020-11-02 15:31:30 -05:00
dcn20_init.c	drm/amd/display: New sequence for HUBP blank	2021-01-13 23:44:22 -05:00
dcn20_init.h	drm/amd/display: cleanup of function pointer tables	2019-11-19 10:12:53 -05:00
dcn20_link_encoder.c	drm/amd/display: Add DIG_CLOCK_PATTERN in the transmitter control	2021-02-09 15:30:42 -05:00
dcn20_link_encoder.h	drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)	2020-11-04 17:11:37 -05:00
dcn20_mmhubbub.c
dcn20_mmhubbub.h	drm/amd/display: Update register defines	2020-02-11 11:50:18 -05:00
dcn20_mpc.c	drm/amd/display: add getter routine to retrieve mpcc mux	2020-12-23 15:02:55 -05:00
dcn20_mpc.h	drm/amd/display: Use cursor locking to prevent flip delays	2020-04-28 16:19:56 -04:00
dcn20_opp.c	drm/amd/display: Raise DPG height during timing synchronization	2020-10-26 13:29:21 -04:00
dcn20_opp.h	drm/amd/display: Raise DPG height during timing synchronization	2020-10-26 13:29:21 -04:00
dcn20_optc.c	drm/amd/display: Fix OPTC_DATA_FORMAT programming	2020-10-05 15:16:57 -04:00
dcn20_optc.h	drm/amd/display: add optc get crc support for timings with ODM/DSC	2020-04-22 18:11:47 -04:00
dcn20_resource.c	drm/amd/display: Add FPU wrappers to dcn21_validate_bandwidth()	2021-02-18 16:43:09 -05:00
dcn20_resource.h	drm/amd/display: Prevent freesync power optimization during validation	2020-11-10 14:24:48 -05:00
dcn20_stream_encoder.c	drm/amd/display: Rename set_mst_bandwidth to align with DP spec	2020-09-15 17:52:41 -04:00
dcn20_stream_encoder.h	drm/amd/display: Add missing DP_SEC register definitions and masks	2020-12-15 11:33:33 -05:00
dcn20_vmid.c
dcn20_vmid.h	drm/amd/display: Update register defines	2020-02-11 11:50:18 -05:00
Makefile	drm/amdgpu/display: drop DCN support for aarch64	2021-01-05 11:35:53 -05:00