7f0b1bf045
The architecture specification states that both DSB and ISB are required between page table modifications and subsequent memory accesses using the corresponding virtual address. When TLB invalidation takes place, the tlb_flush_* functions already have the necessary barriers. However, there are other functions like create_mapping() for which this is not the case. The patch adds the DSB+ISB instructions in the set_pte() function for valid kernel mappings. The invalid pte case is handled by tlb_flush_* and the user mappings in general have a corresponding update_mmu_cache() call containing a DSB. Even when update_mmu_cache() isn't called, the kernel can still cope with an unlikely spurious page fault by re-executing the instruction. In addition, the set_pmd, set_pud() functions gain an ISB for architecture compliance when block mappings are created. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Steve Capper <steve.capper@linaro.org> Cc: Will Deacon <will.deacon@arm.com> Cc: <stable@vger.kernel.org>
146 lines
3.8 KiB
C
146 lines
3.8 KiB
C
/*
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* Based on arch/arm/include/asm/tlbflush.h
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*
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* Copyright (C) 1999-2003 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_TLBFLUSH_H
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#define __ASM_TLBFLUSH_H
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#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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#include <asm/cputype.h>
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extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
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extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
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extern struct cpu_tlb_fns cpu_tlb;
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/*
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* TLB Management
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* ==============
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*
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* The arch/arm64/mm/tlb.S files implement these methods.
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*
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* The TLB specific code is expected to perform whatever tests it needs
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* to determine if it should invalidate the TLB for each call. Start
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* addresses are inclusive and end addresses are exclusive; it is safe to
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* round these addresses down.
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*
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* flush_tlb_all()
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*
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* Invalidate the entire TLB.
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*
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* flush_tlb_mm(mm)
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*
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* Invalidate all TLB entries in a particular address space.
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* - mm - mm_struct describing address space
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*
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* flush_tlb_range(mm,start,end)
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*
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* Invalidate a range of TLB entries in the specified address
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* space.
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* - mm - mm_struct describing address space
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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*
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* flush_tlb_page(vaddr,vma)
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*
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* Invalidate the specified page in the specified address range.
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* - vaddr - virtual address (may not be aligned)
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* - vma - vma_struct describing address range
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*
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* flush_kern_tlb_page(kaddr)
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*
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* Invalidate the TLB entry for the specified page. The address
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* will be in the kernels virtual memory space. Current uses
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* only require the D-TLB to be invalidated.
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* - kaddr - Kernel virtual memory address
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*/
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static inline void flush_tlb_all(void)
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{
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dsb(ishst);
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asm("tlbi vmalle1is");
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dsb(ish);
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isb();
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}
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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unsigned long asid = (unsigned long)ASID(mm) << 48;
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dsb(ishst);
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asm("tlbi aside1is, %0" : : "r" (asid));
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dsb(ish);
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long uaddr)
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{
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unsigned long addr = uaddr >> 12 |
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((unsigned long)ASID(vma->vm_mm) << 48);
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dsb(ishst);
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asm("tlbi vae1is, %0" : : "r" (addr));
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dsb(ish);
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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unsigned long asid = (unsigned long)ASID(vma->vm_mm) << 48;
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unsigned long addr;
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start = asid | (start >> 12);
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end = asid | (end >> 12);
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dsb(ishst);
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for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12))
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asm("tlbi vae1is, %0" : : "r"(addr));
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dsb(ish);
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}
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static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long addr;
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start >>= 12;
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end >>= 12;
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dsb(ishst);
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for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12))
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asm("tlbi vaae1is, %0" : : "r"(addr));
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dsb(ish);
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isb();
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}
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/*
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* On AArch64, the cache coherency is handled via the set_pte_at() function.
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*/
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static inline void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep)
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{
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/*
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* set_pte() does not have a DSB for user mappings, so make sure that
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* the page table write is visible.
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*/
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dsb(ishst);
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}
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#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
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#endif
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#endif
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