forked from Minki/linux
f819b0d4a9
Add DesignWare MIPI DSI Host Controller v1.02 encoder driver for hi6220 SoC. v9: Fix module compile error. v8: None. v7: - A few regs define clean up. v6: - Change "pclk_dsi" to "pclk". v5: None. v4: None. v3: - Rename file name to dw_drm_dsi.c - Make encoder type as DRM_MODE_ENCODER_DSI. - A few cleanup. v2: - Remove abtraction layer. Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org> Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com> Signed-off-by: Andy Green <andy.green@linaro.org>
104 lines
3.6 KiB
C
104 lines
3.6 KiB
C
/*
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* Copyright (c) 2016 Linaro Limited.
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* Copyright (c) 2014-2016 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __DW_DSI_REG_H__
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#define __DW_DSI_REG_H__
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#define MASK(x) (BIT(x) - 1)
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/*
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* regs
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*/
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#define PWR_UP 0x04 /* Core power-up */
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#define RESET 0
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#define POWERUP BIT(0)
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#define PHY_IF_CFG 0xA4 /* D-PHY interface configuration */
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#define CLKMGR_CFG 0x08 /* the internal clock dividers */
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#define PHY_RSTZ 0xA0 /* D-PHY reset control */
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#define PHY_ENABLECLK BIT(2)
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#define PHY_UNRSTZ BIT(1)
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#define PHY_UNSHUTDOWNZ BIT(0)
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#define PHY_TST_CTRL0 0xB4 /* D-PHY test interface control 0 */
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#define PHY_TST_CTRL1 0xB8 /* D-PHY test interface control 1 */
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#define CLK_TLPX 0x10
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#define CLK_THS_PREPARE 0x11
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#define CLK_THS_ZERO 0x12
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#define CLK_THS_TRAIL 0x13
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#define CLK_TWAKEUP 0x14
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#define DATA_TLPX(x) (0x20 + ((x) << 4))
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#define DATA_THS_PREPARE(x) (0x21 + ((x) << 4))
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#define DATA_THS_ZERO(x) (0x22 + ((x) << 4))
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#define DATA_THS_TRAIL(x) (0x23 + ((x) << 4))
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#define DATA_TTA_GO(x) (0x24 + ((x) << 4))
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#define DATA_TTA_GET(x) (0x25 + ((x) << 4))
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#define DATA_TWAKEUP(x) (0x26 + ((x) << 4))
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#define PHY_CFG_I 0x60
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#define PHY_CFG_PLL_I 0x63
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#define PHY_CFG_PLL_II 0x64
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#define PHY_CFG_PLL_III 0x65
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#define PHY_CFG_PLL_IV 0x66
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#define PHY_CFG_PLL_V 0x67
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#define DPI_COLOR_CODING 0x10 /* DPI color coding */
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#define DPI_CFG_POL 0x14 /* DPI polarity configuration */
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#define VID_HSA_TIME 0x48 /* Horizontal Sync Active time */
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#define VID_HBP_TIME 0x4C /* Horizontal Back Porch time */
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#define VID_HLINE_TIME 0x50 /* Line time */
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#define VID_VSA_LINES 0x54 /* Vertical Sync Active period */
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#define VID_VBP_LINES 0x58 /* Vertical Back Porch period */
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#define VID_VFP_LINES 0x5C /* Vertical Front Porch period */
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#define VID_VACTIVE_LINES 0x60 /* Vertical resolution */
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#define VID_PKT_SIZE 0x3C /* Video packet size */
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#define VID_MODE_CFG 0x38 /* Video mode configuration */
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#define PHY_TMR_CFG 0x9C /* Data lanes timing configuration */
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#define BTA_TO_CNT 0x8C /* Response timeout definition */
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#define PHY_TMR_LPCLK_CFG 0x98 /* clock lane timing configuration */
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#define CLK_DATA_TMR_CFG 0xCC
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#define LPCLK_CTRL 0x94 /* Low-power in clock lane */
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#define PHY_TXREQUESTCLKHS BIT(0)
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#define MODE_CFG 0x34 /* Video or Command mode selection */
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#define PHY_STATUS 0xB0 /* D-PHY PPI status interface */
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#define PHY_STOP_WAIT_TIME 0x30
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/*
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* regs relevant enum
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*/
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enum dpi_color_coding {
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DSI_24BITS_1 = 5,
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};
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enum dsi_video_mode_type {
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DSI_NON_BURST_SYNC_PULSES = 0,
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DSI_NON_BURST_SYNC_EVENTS,
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DSI_BURST_SYNC_PULSES_1,
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DSI_BURST_SYNC_PULSES_2
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};
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enum dsi_work_mode {
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DSI_VIDEO_MODE = 0,
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DSI_COMMAND_MODE
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};
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/*
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* Register Write/Read Helper functions
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*/
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static inline void dw_update_bits(void __iomem *addr, u32 bit_start,
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u32 mask, u32 val)
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{
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u32 tmp, orig;
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orig = readl(addr);
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tmp = orig & ~(mask << bit_start);
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tmp |= (val & mask) << bit_start;
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writel(tmp, addr);
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}
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#endif /* __DW_DRM_DSI_H__ */
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