c585132840
The GICv3 backend of the vgic is quite barrier heavy, in order to ensure synchronization of the system registers and the memory mapped view for a potential GICv2 guest. But when the guest is using a GICv3 model, there is absolutely no need to execute all these heavy barriers, and it is actually beneficial to avoid them altogether. This patch makes the synchonization conditional, and ensures that we do not change the EL1 SRE settings if we do not need to. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> |
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| .. | ||
| debug-sr.c | ||
| entry.S | ||
| fpsimd.S | ||
| hyp-entry.S | ||
| Makefile | ||
| s2-setup.c | ||
| switch.c | ||
| sysreg-sr.c | ||
| tlb.c | ||
| vgic-v3-sr.c | ||