forked from Minki/linux
811bb3db25
This has been asked from us already. Prepare for the next time. Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191029163841.5224-2-mika.kuoppala@linux.intel.com
255 lines
5.3 KiB
C
255 lines
5.3 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright <20> 2008-2018 Intel Corporation
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*/
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#ifndef _I915_GPU_ERROR_H_
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#define _I915_GPU_ERROR_H_
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#include <linux/atomic.h>
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#include <linux/kref.h>
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#include <linux/ktime.h>
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#include <linux/sched.h>
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#include <drm/drm_mm.h>
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#include "gt/intel_engine.h"
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#include "gt/uc/intel_uc_fw.h"
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#include "intel_device_info.h"
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#include "i915_gem.h"
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#include "i915_gem_gtt.h"
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#include "i915_params.h"
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#include "i915_scheduler.h"
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struct drm_i915_private;
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struct intel_overlay_error_state;
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struct intel_display_error_state;
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struct i915_gpu_state {
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struct kref ref;
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ktime_t time;
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ktime_t boottime;
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ktime_t uptime;
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unsigned long capture;
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struct drm_i915_private *i915;
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char error_msg[128];
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bool simulated;
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bool awake;
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bool wakelock;
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bool suspended;
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int iommu;
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u32 reset_count;
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u32 suspend_count;
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struct intel_device_info device_info;
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struct intel_runtime_info runtime_info;
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struct intel_driver_caps driver_caps;
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struct i915_params params;
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struct i915_error_uc {
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struct intel_uc_fw guc_fw;
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struct intel_uc_fw huc_fw;
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struct drm_i915_error_object *guc_log;
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} uc;
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/* Generic register state */
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u32 eir;
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u32 pgtbl_er;
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u32 ier;
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u32 gtier[6], ngtier;
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u32 ccid;
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u32 derrmr;
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u32 forcewake;
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u32 error; /* gen6+ */
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u32 err_int; /* gen7 */
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u32 fault_data0; /* gen8, gen9 */
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u32 fault_data1; /* gen8, gen9 */
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u32 done_reg;
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u32 gac_eco;
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u32 gam_ecochk;
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u32 gab_ctl;
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u32 gfx_mode;
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u32 gtt_cache;
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u32 aux_err; /* gen12 */
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u32 sfc_done[GEN12_SFC_DONE_MAX]; /* gen12 */
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u32 gam_done; /* gen12 */
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u32 nfence;
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u64 fence[I915_MAX_NUM_FENCES];
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struct intel_overlay_error_state *overlay;
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struct intel_display_error_state *display;
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struct drm_i915_error_engine {
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const struct intel_engine_cs *engine;
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/* Software tracked state */
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bool idle;
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int num_requests;
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u32 reset_count;
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/* position of active request inside the ring */
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u32 rq_head, rq_post, rq_tail;
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/* our own tracking of ring head and tail */
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u32 cpu_ring_head;
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u32 cpu_ring_tail;
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/* Register state */
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u32 start;
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u32 tail;
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u32 head;
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u32 ctl;
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u32 mode;
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u32 hws;
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u32 ipeir;
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u32 ipehr;
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u32 bbstate;
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u32 instpm;
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u32 instps;
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u64 bbaddr;
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u64 acthd;
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u32 fault_reg;
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u64 faddr;
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u32 rc_psmi; /* sleep state */
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struct intel_instdone instdone;
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struct drm_i915_error_context {
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char comm[TASK_COMM_LEN];
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pid_t pid;
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int active;
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int guilty;
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struct i915_sched_attr sched_attr;
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} context;
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struct drm_i915_error_object {
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u64 gtt_offset;
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u64 gtt_size;
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u32 gtt_page_sizes;
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int num_pages;
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int page_count;
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int unused;
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u32 *pages[0];
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} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
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struct drm_i915_error_object **user_bo;
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long user_bo_count;
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struct drm_i915_error_object *wa_ctx;
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struct drm_i915_error_object *default_state;
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struct drm_i915_error_request {
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unsigned long flags;
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long jiffies;
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pid_t pid;
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u32 context;
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u32 seqno;
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u32 start;
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u32 head;
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u32 tail;
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struct i915_sched_attr sched_attr;
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} *requests, execlist[EXECLIST_MAX_PORTS];
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unsigned int num_ports;
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struct {
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u32 gfx_mode;
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union {
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u64 pdp[4];
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u32 pp_dir_base;
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};
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} vm_info;
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struct drm_i915_error_engine *next;
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} *engine;
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struct scatterlist *sgl, *fit;
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};
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struct i915_gpu_error {
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/* For reset and error_state handling. */
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spinlock_t lock;
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/* Protected by the above dev->gpu_error.lock. */
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struct i915_gpu_state *first_error;
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atomic_t pending_fb_pin;
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/** Number of times the device has been reset (global) */
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atomic_t reset_count;
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/** Number of times an engine has been reset */
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atomic_t reset_engine_count[I915_NUM_ENGINES];
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};
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struct drm_i915_error_state_buf {
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struct drm_i915_private *i915;
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struct scatterlist *sgl, *cur, *end;
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char *buf;
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size_t bytes;
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size_t size;
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loff_t iter;
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int err;
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};
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#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
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__printf(2, 3)
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void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
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struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
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void i915_capture_error_state(struct drm_i915_private *dev_priv,
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intel_engine_mask_t engine_mask,
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const char *error_msg);
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static inline struct i915_gpu_state *
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i915_gpu_state_get(struct i915_gpu_state *gpu)
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{
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kref_get(&gpu->ref);
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return gpu;
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}
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ssize_t i915_gpu_state_copy_to_buffer(struct i915_gpu_state *error,
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char *buf, loff_t offset, size_t count);
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void __i915_gpu_state_free(struct kref *kref);
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static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
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{
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if (gpu)
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kref_put(&gpu->ref, __i915_gpu_state_free);
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}
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struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
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void i915_reset_error_state(struct drm_i915_private *i915);
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void i915_disable_error_state(struct drm_i915_private *i915, int err);
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#else
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static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
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u32 engine_mask,
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const char *error_msg)
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{
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}
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static inline struct i915_gpu_state *
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i915_first_error_state(struct drm_i915_private *i915)
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{
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return ERR_PTR(-ENODEV);
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}
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static inline void i915_reset_error_state(struct drm_i915_private *i915)
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{
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}
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static inline void i915_disable_error_state(struct drm_i915_private *i915,
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int err)
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{
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}
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#endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
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#endif /* _I915_GPU_ERROR_H_ */
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