Dan Williams 7d4b5ca2e2 cxl/acpi: Add downstream port data to cxl_port instances ... In preparation for infrastructure that enumerates and configures the CXL decode mechanism of an upstream port to its downstream ports, add a representation of a CXL downstream port. On ACPI systems the top-most logical downstream ports in the hierarchy are the host bridges (ACPI0016 devices) that decode the memory windows described by the CXL Early Discovery Table Fixed Memory Window Structures (CEDT.CFMWS). Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://lore.kernel.org/r/162325450624.2293126.3533006409920271718.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2021-06-09 18:02:39 -07:00
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acpi.c	cxl/acpi: Add downstream port data to cxl_port instances	2021-06-09 18:02:39 -07:00
core.c	cxl/acpi: Add downstream port data to cxl_port instances	2021-06-09 18:02:39 -07:00
cxl.h	cxl/acpi: Add downstream port data to cxl_port instances	2021-06-09 18:02:39 -07:00
Kconfig	cxl/Kconfig: Default drivers to CONFIG_CXL_BUS	2021-06-09 18:02:38 -07:00
Makefile	cxl/acpi: Introduce the root of a cxl_port topology	2021-06-09 18:02:38 -07:00
mem.h	cxl/mem: Get rid of @cxlm.base	2021-05-26 11:20:18 -07:00
pci.c	cxl/pci: Add HDM decoder capabilities	2021-06-05 17:39:12 -07:00
pci.h