Andrew Jeffery 7d29ed88ac pinctrl: aspeed: Read and write bits in LPC and GFX controllers ... The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these as necessary. We use syscon to cast a regmap over the GFX and LPC blocks, which is used as an arbitration layer between the relevant driver and the pinctrl subsystem. The regmaps are then exposed to the SoC-specific pinctrl drivers by phandles in the devicetree, and are selected during a mux request by querying a new 'ip' member in struct aspeed_sig_desc. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>		2016-12-27 23:15:32 +01:00
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Kconfig	pinctrl: Add pinctrl-aspeed-g5 driver	2016-09-07 16:53:37 +02:00
Makefile	pinctrl: Add pinctrl-aspeed-g5 driver	2016-09-07 16:53:37 +02:00
pinctrl-aspeed-g4.c	pinctrl: aspeed: Read and write bits in LPC and GFX controllers	2016-12-27 23:15:32 +01:00
pinctrl-aspeed-g5.c	pinctrl: aspeed: Read and write bits in LPC and GFX controllers	2016-12-27 23:15:32 +01:00
pinctrl-aspeed.c	pinctrl: aspeed: Read and write bits in LPC and GFX controllers	2016-12-27 23:15:32 +01:00
pinctrl-aspeed.h	pinctrl: aspeed: Read and write bits in LPC and GFX controllers	2016-12-27 23:15:32 +01:00