7c5925afbc
Implement a multiplexed IRQ domain hierarchy API in the pcie-designware host bridge driver that funnels all MSI IRQs into a single parent interrupt, moving away from the obsolete struct msi_controller based API. Although the old implementation API is still available, pcie-designware will now use the multiplexed IRQ domains hierarchical API. Remove all existing dwc based host bridges MSI IRQs handlers, in that the hierarchical API now handles MSI IRQs through the hierarchical/chained MSI domain implementation. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Niklas Cassel <niklas.cassel@axis.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
59 lines
2.1 KiB
C
59 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Keystone PCI Controller's common includes
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*
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* Copyright (C) 2013-2014 Texas Instruments., Ltd.
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* http://www.ti.com
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*
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* Author: Murali Karicheri <m-karicheri2@ti.com>
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*/
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#define MAX_MSI_HOST_IRQS 8
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struct keystone_pcie {
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struct dw_pcie *pci;
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struct clk *clk;
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/* PCI Device ID */
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u32 device_id;
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int num_legacy_host_irqs;
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int legacy_host_irqs[PCI_NUM_INTX];
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struct device_node *legacy_intc_np;
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int num_msi_host_irqs;
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int msi_host_irqs[MAX_MSI_HOST_IRQS];
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struct device_node *msi_intc_np;
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struct irq_domain *legacy_irq_domain;
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struct device_node *np;
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int error_irq;
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/* Application register space */
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void __iomem *va_app_base; /* DT 1st resource */
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struct resource app;
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};
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/* Keystone DW specific MSI controller APIs/definitions */
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void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset);
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phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);
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/* Keystone specific PCI controller APIs */
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void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);
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void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset);
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void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie);
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irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie);
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int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
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struct device_node *msi_intc_np);
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int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 val);
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int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 *val);
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void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
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void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
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void ks_dw_pcie_msi_irq_ack(int i, struct pcie_port *pp);
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void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
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void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
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void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
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int ks_dw_pcie_msi_host_init(struct pcie_port *pp,
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struct msi_controller *chip);
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int ks_dw_pcie_link_up(struct dw_pcie *pci);
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