forked from Minki/linux
5ec1d441a4
Since e4b3d38088 ("phy: exynos-video-mipi: Fix regression by adding
support for PMU regmap") the Exynos PMU driver provides regmap to access
the MIPI DPHY registers. The MIPI DPHY driver accesses this regmap
through syscon phandle.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
639 lines
15 KiB
Plaintext
639 lines
15 KiB
Plaintext
/*
|
|
* Samsung's Exynos4415 SoC device tree source
|
|
*
|
|
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
|
*
|
|
* Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415
|
|
* based board files can include this file and provide values for board
|
|
* specific bindings.
|
|
*
|
|
* Note: This file does not include device nodes for all the controllers in
|
|
* Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional
|
|
* nodes can be added to this file.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include "skeleton.dtsi"
|
|
#include <dt-bindings/clock/exynos4415.h>
|
|
#include <dt-bindings/clock/exynos-audss-clk.h>
|
|
|
|
/ {
|
|
compatible = "samsung,exynos4415";
|
|
interrupt-parent = <&gic>;
|
|
|
|
aliases {
|
|
pinctrl0 = &pinctrl_0;
|
|
pinctrl1 = &pinctrl_1;
|
|
pinctrl2 = &pinctrl_2;
|
|
mshc0 = &mshc_0;
|
|
mshc1 = &mshc_1;
|
|
mshc2 = &mshc_2;
|
|
spi0 = &spi_0;
|
|
spi1 = &spi_1;
|
|
spi2 = &spi_2;
|
|
i2c0 = &i2c_0;
|
|
i2c1 = &i2c_1;
|
|
i2c2 = &i2c_2;
|
|
i2c3 = &i2c_3;
|
|
i2c4 = &i2c_4;
|
|
i2c5 = &i2c_5;
|
|
i2c6 = &i2c_6;
|
|
i2c7 = &i2c_7;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@a00 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <0xa00>;
|
|
clock-frequency = <1600000000>;
|
|
};
|
|
|
|
cpu1: cpu@a01 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <0xa01>;
|
|
clock-frequency = <1600000000>;
|
|
};
|
|
|
|
cpu2: cpu@a02 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <0xa02>;
|
|
clock-frequency = <1600000000>;
|
|
};
|
|
|
|
cpu3: cpu@a03 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <0xa03>;
|
|
clock-frequency = <1600000000>;
|
|
};
|
|
};
|
|
|
|
soc: soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
sysram@02020000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x02020000 0x50000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x02020000 0x50000>;
|
|
|
|
smp-sysram@0 {
|
|
compatible = "samsung,exynos4210-sysram";
|
|
reg = <0x0 0x1000>;
|
|
};
|
|
|
|
smp-sysram@4f000 {
|
|
compatible = "samsung,exynos4210-sysram-ns";
|
|
reg = <0x4f000 0x1000>;
|
|
};
|
|
};
|
|
|
|
pinctrl_2: pinctrl@03860000 {
|
|
compatible = "samsung,exynos4415-pinctrl";
|
|
reg = <0x03860000 0x1000>;
|
|
interrupts = <0 242 0>;
|
|
};
|
|
|
|
chipid@10000000 {
|
|
compatible = "samsung,exynos4210-chipid";
|
|
reg = <0x10000000 0x100>;
|
|
};
|
|
|
|
sysreg_system_controller: syscon@10010000 {
|
|
compatible = "samsung,exynos4-sysreg", "syscon";
|
|
reg = <0x10010000 0x400>;
|
|
};
|
|
|
|
pmu_system_controller: system-controller@10020000 {
|
|
compatible = "samsung,exynos4415-pmu", "syscon";
|
|
reg = <0x10020000 0x4000>;
|
|
};
|
|
|
|
mipi_phy: video-phy@10020710 {
|
|
compatible = "samsung,s5pv210-mipi-video-phy";
|
|
#phy-cells = <1>;
|
|
syscon = <&pmu_system_controller>;
|
|
};
|
|
|
|
pd_cam: cam-power-domain@10024000 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10024000 0x20>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_tv: tv-power-domain@10024020 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10024020 0x20>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_mfc: mfc-power-domain@10024040 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10024040 0x20>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_g3d: g3d-power-domain@10024060 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10024060 0x20>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_lcd0: lcd0-power-domain@10024080 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10024080 0x20>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_isp0: isp0-power-domain@100240A0 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x100240A0 0x20>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_isp1: isp1-power-domain@100240E0 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x100240E0 0x20>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
cmu: clock-controller@10030000 {
|
|
compatible = "samsung,exynos4415-cmu";
|
|
reg = <0x10030000 0x18000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
rtc: rtc@10070000 {
|
|
compatible = "samsung,s3c6410-rtc";
|
|
reg = <0x10070000 0x100>;
|
|
interrupts = <0 73 0>, <0 74 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mct@10050000 {
|
|
compatible = "samsung,exynos4210-mct";
|
|
reg = <0x10050000 0x800>;
|
|
interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
|
|
<0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
|
|
clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
|
|
clock-names = "fin_pll", "mct";
|
|
};
|
|
|
|
gic: interrupt-controller@10481000 {
|
|
compatible = "arm,cortex-a9-gic";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
reg = <0x10481000 0x1000>,
|
|
<0x10482000 0x1000>,
|
|
<0x10484000 0x2000>,
|
|
<0x10486000 0x2000>;
|
|
interrupts = <1 9 0xf04>;
|
|
};
|
|
|
|
l2c: l2-cache-controller@10502000 {
|
|
compatible = "arm,pl310-cache";
|
|
reg = <0x10502000 0x1000>;
|
|
cache-unified;
|
|
cache-level = <2>;
|
|
arm,tag-latency = <2 2 1>;
|
|
arm,data-latency = <3 2 1>;
|
|
arm,double-linefill = <1>;
|
|
arm,double-linefill-incr = <0>;
|
|
arm,double-linefill-wrap = <1>;
|
|
arm,prefetch-drop = <1>;
|
|
arm,prefetch-offset = <7>;
|
|
};
|
|
|
|
cmu_dmc: clock-controller@105C0000 {
|
|
compatible = "samsung,exynos4415-cmu-dmc";
|
|
reg = <0x105C0000 0x3000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
pinctrl_1: pinctrl@11000000 {
|
|
compatible = "samsung,exynos4415-pinctrl";
|
|
reg = <0x11000000 0x1000>;
|
|
interrupts = <0 225 0>;
|
|
|
|
wakeup-interrupt-controller {
|
|
compatible = "samsung,exynos4210-wakeup-eint";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 48 0>;
|
|
};
|
|
};
|
|
|
|
pinctrl_0: pinctrl@11400000 {
|
|
compatible = "samsung,exynos4415-pinctrl";
|
|
reg = <0x11400000 0x1000>;
|
|
interrupts = <0 240 0>;
|
|
};
|
|
|
|
fimd: fimd@11C00000 {
|
|
compatible = "samsung,exynos4415-fimd";
|
|
reg = <0x11C00000 0x30000>;
|
|
interrupt-names = "fifo", "vsync", "lcd_sys";
|
|
interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
|
|
clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
|
|
clock-names = "sclk_fimd", "fimd";
|
|
samsung,power-domain = <&pd_lcd0>;
|
|
samsung,sysreg = <&sysreg_system_controller>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dsi_0: dsi@11C80000 {
|
|
compatible = "samsung,exynos4415-mipi-dsi";
|
|
reg = <0x11C80000 0x10000>;
|
|
interrupts = <0 83 0>;
|
|
samsung,phy-type = <0>;
|
|
samsung,power-domain = <&pd_lcd0>;
|
|
phys = <&mipi_phy 1>;
|
|
phy-names = "dsim";
|
|
clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
|
|
clock-names = "bus_clk", "pll_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hsotg: hsotg@12480000 {
|
|
compatible = "samsung,s3c6400-hsotg";
|
|
reg = <0x12480000 0x20000>;
|
|
interrupts = <0 141 0>;
|
|
clocks = <&cmu CLK_USBDEVICE>;
|
|
clock-names = "otg";
|
|
phys = <&exynos_usbphy 0>;
|
|
phy-names = "usb2-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
mshc_0: mshc@12510000 {
|
|
compatible = "samsung,exynos5250-dw-mshc";
|
|
reg = <0x12510000 0x1000>;
|
|
interrupts = <0 142 0>;
|
|
clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
|
|
clock-names = "biu", "ciu";
|
|
fifo-depth = <0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mshc_1: mshc@12520000 {
|
|
compatible = "samsung,exynos5250-dw-mshc";
|
|
reg = <0x12520000 0x1000>;
|
|
interrupts = <0 143 0>;
|
|
clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
|
|
clock-names = "biu", "ciu";
|
|
fifo-depth = <0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mshc_2: mshc@12530000 {
|
|
compatible = "samsung,exynos5250-dw-mshc";
|
|
reg = <0x12530000 0x1000>;
|
|
interrupts = <0 144 0>;
|
|
clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
|
|
clock-names = "biu", "ciu";
|
|
fifo-depth = <0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci: ehci@12580000 {
|
|
compatible = "samsung,exynos4210-ehci";
|
|
reg = <0x12580000 0x100>;
|
|
interrupts = <0 140 0>;
|
|
clocks = <&cmu CLK_USBHOST>;
|
|
clock-names = "usbhost";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@0 {
|
|
reg = <0>;
|
|
phys = <&exynos_usbphy 1>;
|
|
status = "disabled";
|
|
};
|
|
port@1 {
|
|
reg = <1>;
|
|
phys = <&exynos_usbphy 2>;
|
|
status = "disabled";
|
|
};
|
|
port@2 {
|
|
reg = <2>;
|
|
phys = <&exynos_usbphy 3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
ohci: ohci@12590000 {
|
|
compatible = "samsung,exynos4210-ohci";
|
|
reg = <0x12590000 0x100>;
|
|
interrupts = <0 140 0>;
|
|
clocks = <&cmu CLK_USBHOST>;
|
|
clock-names = "usbhost";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@0 {
|
|
reg = <0>;
|
|
phys = <&exynos_usbphy 1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
exynos_usbphy: exynos-usbphy@125B0000 {
|
|
compatible = "samsung,exynos4x12-usb2-phy";
|
|
reg = <0x125B0000 0x100>;
|
|
samsung,pmureg-phandle = <&pmu_system_controller>;
|
|
samsung,sysreg-phandle = <&sysreg_system_controller>;
|
|
clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
|
|
clock-names = "phy", "ref";
|
|
#phy-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
amba {
|
|
compatible = "arm,amba-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
ranges;
|
|
|
|
pdma0: pdma@12680000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x12680000 0x1000>;
|
|
interrupts = <0 138 0>;
|
|
clocks = <&cmu CLK_PDMA0>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
#dma-channels = <8>;
|
|
#dma-requests = <32>;
|
|
};
|
|
|
|
pdma1: pdma@12690000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x12690000 0x1000>;
|
|
interrupts = <0 139 0>;
|
|
clocks = <&cmu CLK_PDMA1>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
#dma-channels = <8>;
|
|
#dma-requests = <32>;
|
|
};
|
|
};
|
|
|
|
adc: adc@126C0000 {
|
|
compatible = "samsung,exynos3250-adc",
|
|
"samsung,exynos-adc-v2";
|
|
reg = <0x126C0000 0x100>, <0x10020718 0x4>;
|
|
interrupts = <0 137 0>;
|
|
clock-names = "adc", "sclk";
|
|
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
|
|
#io-channel-cells = <1>;
|
|
io-channel-ranges;
|
|
status = "disabled";
|
|
};
|
|
|
|
serial_0: serial@13800000 {
|
|
compatible = "samsung,exynos4210-uart";
|
|
reg = <0x13800000 0x100>;
|
|
interrupts = <0 109 0>;
|
|
clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
status = "disabled";
|
|
};
|
|
|
|
serial_1: serial@13810000 {
|
|
compatible = "samsung,exynos4210-uart";
|
|
reg = <0x13810000 0x100>;
|
|
interrupts = <0 110 0>;
|
|
clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
status = "disabled";
|
|
};
|
|
|
|
serial_2: serial@13820000 {
|
|
compatible = "samsung,exynos4210-uart";
|
|
reg = <0x13820000 0x100>;
|
|
interrupts = <0 111 0>;
|
|
clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
status = "disabled";
|
|
};
|
|
|
|
serial_3: serial@13830000 {
|
|
compatible = "samsung,exynos4210-uart";
|
|
reg = <0x13830000 0x100>;
|
|
interrupts = <0 112 0>;
|
|
clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_0: i2c@13860000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x13860000 0x100>;
|
|
interrupts = <0 113 0>;
|
|
clocks = <&cmu CLK_I2C0>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_1: i2c@13870000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x13870000 0x100>;
|
|
interrupts = <0 114 0>;
|
|
clocks = <&cmu CLK_I2C1>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_2: i2c@13880000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x13880000 0x100>;
|
|
interrupts = <0 115 0>;
|
|
clocks = <&cmu CLK_I2C2>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_3: i2c@13890000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x13890000 0x100>;
|
|
interrupts = <0 116 0>;
|
|
clocks = <&cmu CLK_I2C3>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_4: i2c@138A0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x138A0000 0x100>;
|
|
interrupts = <0 117 0>;
|
|
clocks = <&cmu CLK_I2C4>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_5: i2c@138B0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x138B0000 0x100>;
|
|
interrupts = <0 118 0>;
|
|
clocks = <&cmu CLK_I2C5>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_6: i2c@138C0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x138C0000 0x100>;
|
|
interrupts = <0 119 0>;
|
|
clocks = <&cmu CLK_I2C6>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_7: i2c@138D0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x138D0000 0x100>;
|
|
interrupts = <0 120 0>;
|
|
clocks = <&cmu CLK_I2C7>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c7_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_0: spi@13920000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x13920000 0x100>;
|
|
interrupts = <0 121 0>;
|
|
dmas = <&pdma0 7>, <&pdma0 6>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
samsung,spi-src-clk = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_1: spi@13930000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x13930000 0x100>;
|
|
interrupts = <0 122 0>;
|
|
dmas = <&pdma1 7>, <&pdma1 6>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
samsung,spi-src-clk = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_2: spi@13940000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x13940000 0x100>;
|
|
interrupts = <0 123 0>;
|
|
dmas = <&pdma0 9>, <&pdma0 8>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
samsung,spi-src-clk = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi2_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
clock_audss: clock-controller@03810000 {
|
|
compatible = "samsung,exynos4210-audss-clock";
|
|
reg = <0x03810000 0x0C>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
i2s0: i2s@3830000 {
|
|
compatible = "samsung,s5pv210-i2s";
|
|
reg = <0x03830000 0x100>;
|
|
interrupts = <0 124 0>;
|
|
clocks = <&clock_audss EXYNOS_I2S_BUS>,
|
|
<&clock_audss EXYNOS_SCLK_I2S>;
|
|
clock-names = "iis", "i2s_opclk0";
|
|
dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>;
|
|
dma-names = "tx", "rx", "tx-sec";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s0_bus>;
|
|
samsung,idma-addr = <0x03000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@139D0000 {
|
|
compatible = "samsung,exynos4210-pwm";
|
|
reg = <0x139D0000 0x1000>;
|
|
interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
|
|
<0 107 0>, <0 108 0>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a9-pmu";
|
|
interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "exynos4415-pinctrl.dtsi"
|