forked from Minki/linux
9954119536
This patch updates the common platform files with AM335X device support (AM33XX family). The approach taken in this patch is, AM33XX device will be considered as OMAP3 variant, and a separate SoC class created for AM33XX family of devices with a subclass type for AM335X device, which is newly added device in the family. This means, cpu_is_omap34xx(), cpu_is_am33xx() and cpu_is_am335x() checks will return success on AM335X device. A kernel config option CONFIG_SOC_OMAPAM33XX is added under OMAP3 to include support for AM33XX build. Also, cpu_mask and RATE_IN_XXX flags have crossed 8 bit hence struct clksel_rate.flags, struct prcm_config.flags and cpu_mask are changed to u16 from u8. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Hemant Pedanekar <hemantp@ti.com> [tony@atomide.com: left out CK_AM33XX for now] Signed-off-by: Tony Lindgren <tony@atomide.com>
167 lines
5.5 KiB
C
167 lines
5.5 KiB
C
/*
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* linux/arch/arm/mach-omap2/clock.h
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*
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* Copyright (C) 2005-2009 Texas Instruments, Inc.
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* Copyright (C) 2004-2011 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
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#include <linux/kernel.h>
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#include <plat/clock.h>
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/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
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#define CORE_CLK_SRC_32K 0x0
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#define CORE_CLK_SRC_DPLL 0x1
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#define CORE_CLK_SRC_DPLL_X2 0x2
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/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
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#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
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#define OMAP2XXX_EN_DPLL_LOCKED 0x3
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/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
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#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP3XXX_EN_DPLL_LOCKED 0x7
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/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
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#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
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#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP4XXX_EN_DPLL_LOCKED 0x7
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/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
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#define DPLL_LOW_POWER_STOP 0x1
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#define DPLL_LOW_POWER_BYPASS 0x5
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#define DPLL_LOCKED 0x7
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/* DPLL Type and DCO Selection Flags */
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#define DPLL_J_TYPE 0x1
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int omap2_clk_enable(struct clk *clk);
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void omap2_clk_disable(struct clk *clk);
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long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
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int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
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int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
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long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
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unsigned long omap3_dpll_recalc(struct clk *clk);
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unsigned long omap3_clkoutx2_recalc(struct clk *clk);
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void omap3_dpll_allow_idle(struct clk *clk);
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void omap3_dpll_deny_idle(struct clk *clk);
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u32 omap3_dpll_autoidle_read(struct clk *clk);
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int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
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int omap3_noncore_dpll_enable(struct clk *clk);
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void omap3_noncore_dpll_disable(struct clk *clk);
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int omap4_dpllmx_gatectrl_read(struct clk *clk);
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void omap4_dpllmx_allow_gatectrl(struct clk *clk);
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void omap4_dpllmx_deny_gatectrl(struct clk *clk);
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long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate);
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unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk);
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#ifdef CONFIG_OMAP_RESET_CLOCKS
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void omap2_clk_disable_unused(struct clk *clk);
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#else
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#define omap2_clk_disable_unused NULL
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#endif
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void omap2_init_clk_clkdm(struct clk *clk);
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void __init omap2_clk_disable_clkdm_control(void);
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/* clkt_clksel.c public functions */
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u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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u32 *new_div);
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void omap2_init_clksel_parent(struct clk *clk);
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unsigned long omap2_clksel_recalc(struct clk *clk);
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long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
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int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
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int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
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/* clkt_iclk.c public functions */
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extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
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extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
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u32 omap2_get_dpll_rate(struct clk *clk);
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void omap2_init_dpll_parent(struct clk *clk);
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int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
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#ifdef CONFIG_ARCH_OMAP2
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void omap2xxx_clk_prepare_for_reboot(void);
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#else
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static inline void omap2xxx_clk_prepare_for_reboot(void)
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{
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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void omap3_clk_prepare_for_reboot(void);
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#else
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static inline void omap3_clk_prepare_for_reboot(void)
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{
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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void omap4_clk_prepare_for_reboot(void);
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#else
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static inline void omap4_clk_prepare_for_reboot(void)
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{
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}
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#endif
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int omap2_dflt_clk_enable(struct clk *clk);
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void omap2_dflt_clk_disable(struct clk *clk);
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void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
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u8 *other_bit);
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void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
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u8 *idlest_bit, u8 *idlest_val);
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int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
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void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
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const char *core_ck_name,
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const char *mpu_ck_name);
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extern u16 cpu_mask;
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extern const struct clkops clkops_omap2_dflt_wait;
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extern const struct clkops clkops_dummy;
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extern const struct clkops clkops_omap2_dflt;
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extern struct clk_functions omap2_clk_functions;
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extern struct clk *vclk, *sclk;
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extern const struct clksel_rate gpt_32k_rates[];
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extern const struct clksel_rate gpt_sys_rates[];
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extern const struct clksel_rate gfx_l3_rates[];
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extern const struct clksel_rate dsp_ick_rates[];
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#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
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extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
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extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
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#else
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#define omap2_clk_init_cpufreq_table 0
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#define omap2_clk_exit_cpufreq_table 0
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#endif
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extern const struct clkops clkops_omap2_iclk_dflt_wait;
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extern const struct clkops clkops_omap2_iclk_dflt;
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extern const struct clkops clkops_omap2_iclk_idle_only;
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extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
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extern const struct clkops clkops_omap2xxx_dpll_ops;
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extern const struct clkops clkops_omap3_noncore_dpll_ops;
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extern const struct clkops clkops_omap3_core_dpll_ops;
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extern const struct clkops clkops_omap4_dpllmx_ops;
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#endif
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