7bdc072086
As vendor document indicate, when REF_CLK bit set 0, then DP phy's REF_CLK should switch to 24M source clock. But due to IC PHY layout mistaken, some chips need to flip this bit(like RK3288), and unfortunately they didn't indicate in the DP version register. That's why we have to make this little hack. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> |
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| .. | ||
| analogix | ||
| analogix-anx78xx.c | ||
| analogix-anx78xx.h | ||
| dw-hdmi-ahb-audio.c | ||
| dw-hdmi-audio.h | ||
| dw-hdmi.c | ||
| dw-hdmi.h | ||
| Kconfig | ||
| Makefile | ||
| nxp-ptn3460.c | ||
| parade-ps8622.c | ||
| sii902x.c | ||