forked from Minki/linux
cad5cef62a
CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, __devinitconst, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
800 lines
23 KiB
C
800 lines
23 KiB
C
/*
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* MPC5200 General Purpose Timer device driver
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*
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* Copyright (c) 2009 Secret Lab Technologies Ltd.
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* Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This file is a driver for the the General Purpose Timer (gpt) devices
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* found on the MPC5200 SoC. Each timer has an IO pin which can be used
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* for GPIO or can be used to raise interrupts. The timer function can
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* be used independently from the IO pin, or it can be used to control
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* output signals or measure input signals.
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*
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* This driver supports the GPIO and IRQ controller functions of the GPT
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* device. Timer functions are not yet supported.
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*
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* The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used,
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* this prevents the use of any gpt0 gpt function (i.e. they will fail with
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* -EBUSY). Thus, the safety wdt function always has precedence over the gpt
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* function. If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT,
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* this means that gpt0 is locked in wdt mode until the next reboot - this
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* may be a requirement in safety applications.
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*
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* To use the GPIO function, the following two properties must be added
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* to the device tree node for the gpt device (typically in the .dts file
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* for the board):
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* gpio-controller;
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* #gpio-cells = < 2 >;
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* This driver will register the GPIO pin if it finds the gpio-controller
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* property in the device tree.
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*
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* To use the IRQ controller function, the following two properties must
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* be added to the device tree node for the gpt device:
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* interrupt-controller;
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* #interrupt-cells = < 1 >;
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* The IRQ controller binding only uses one cell to specify the interrupt,
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* and the IRQ flags are encoded in the cell. A cell is not used to encode
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* the IRQ number because the GPT only has a single IRQ source. For flags,
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* a value of '1' means rising edge sensitive and '2' means falling edge.
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*
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* The GPIO and the IRQ controller functions can be used at the same time,
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* but in this use case the IO line will only work as an input. Trying to
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* use it as a GPIO output will not work.
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*
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* When using the GPIO line as an output, it can either be driven as normal
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* IO, or it can be an Open Collector (OC) output. At the moment it is the
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* responsibility of either the bootloader or the platform setup code to set
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* the output mode. This driver does not change the output mode setting.
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*/
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#include <linux/device.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_gpio.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/fs.h>
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#include <linux/watchdog.h>
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#include <linux/miscdevice.h>
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#include <linux/uaccess.h>
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#include <linux/module.h>
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#include <asm/div64.h>
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#include <asm/mpc52xx.h>
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MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
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MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß");
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MODULE_LICENSE("GPL");
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/**
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* struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
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* @dev: pointer to device structure
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* @regs: virtual address of GPT registers
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* @lock: spinlock to coordinate between different functions.
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* @gc: gpio_chip instance structure; used when GPIO is enabled
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* @irqhost: Pointer to irq_domain instance; used when IRQ mode is supported
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* @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
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* if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
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* if the timer is actively used as wdt which blocks gpt functions
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*/
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struct mpc52xx_gpt_priv {
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struct list_head list; /* List of all GPT devices */
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struct device *dev;
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struct mpc52xx_gpt __iomem *regs;
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spinlock_t lock;
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struct irq_domain *irqhost;
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u32 ipb_freq;
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u8 wdt_mode;
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#if defined(CONFIG_GPIOLIB)
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struct gpio_chip gc;
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#endif
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};
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LIST_HEAD(mpc52xx_gpt_list);
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DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
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#define MPC52xx_GPT_MODE_MS_MASK (0x07)
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#define MPC52xx_GPT_MODE_MS_IC (0x01)
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#define MPC52xx_GPT_MODE_MS_OC (0x02)
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#define MPC52xx_GPT_MODE_MS_PWM (0x03)
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#define MPC52xx_GPT_MODE_MS_GPIO (0x04)
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#define MPC52xx_GPT_MODE_GPIO_MASK (0x30)
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#define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20)
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#define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30)
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#define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000)
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#define MPC52xx_GPT_MODE_CONTINUOUS (0x0400)
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#define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200)
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#define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
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#define MPC52xx_GPT_MODE_WDT_EN (0x8000)
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#define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
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#define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
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#define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
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#define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
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#define MPC52xx_GPT_MODE_WDT_PING (0xa5)
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#define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
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#define MPC52xx_GPT_CAN_WDT (1 << 0)
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#define MPC52xx_GPT_IS_WDT (1 << 1)
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/* ---------------------------------------------------------------------
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* Cascaded interrupt controller hooks
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*/
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static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
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{
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struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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spin_lock_irqsave(&gpt->lock, flags);
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setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
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spin_unlock_irqrestore(&gpt->lock, flags);
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}
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static void mpc52xx_gpt_irq_mask(struct irq_data *d)
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{
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struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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spin_lock_irqsave(&gpt->lock, flags);
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clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
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spin_unlock_irqrestore(&gpt->lock, flags);
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}
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static void mpc52xx_gpt_irq_ack(struct irq_data *d)
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{
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struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
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out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
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}
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static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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u32 reg;
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dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type);
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spin_lock_irqsave(&gpt->lock, flags);
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reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
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if (flow_type & IRQF_TRIGGER_RISING)
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reg |= MPC52xx_GPT_MODE_ICT_RISING;
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if (flow_type & IRQF_TRIGGER_FALLING)
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reg |= MPC52xx_GPT_MODE_ICT_FALLING;
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out_be32(&gpt->regs->mode, reg);
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spin_unlock_irqrestore(&gpt->lock, flags);
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return 0;
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}
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static struct irq_chip mpc52xx_gpt_irq_chip = {
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.name = "MPC52xx GPT",
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.irq_unmask = mpc52xx_gpt_irq_unmask,
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.irq_mask = mpc52xx_gpt_irq_mask,
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.irq_ack = mpc52xx_gpt_irq_ack,
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.irq_set_type = mpc52xx_gpt_irq_set_type,
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};
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void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc)
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{
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struct mpc52xx_gpt_priv *gpt = irq_get_handler_data(virq);
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int sub_virq;
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u32 status;
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status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
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if (status) {
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sub_virq = irq_linear_revmap(gpt->irqhost, 0);
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generic_handle_irq(sub_virq);
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}
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}
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static int mpc52xx_gpt_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct mpc52xx_gpt_priv *gpt = h->host_data;
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dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
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irq_set_chip_data(virq, gpt);
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irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
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return 0;
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}
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static int mpc52xx_gpt_irq_xlate(struct irq_domain *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_flags)
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{
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struct mpc52xx_gpt_priv *gpt = h->host_data;
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dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
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if ((intsize < 1) || (intspec[0] > 3)) {
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dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name);
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return -EINVAL;
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}
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*out_hwirq = 0; /* The GPT only has 1 IRQ line */
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*out_flags = intspec[0];
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return 0;
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}
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static const struct irq_domain_ops mpc52xx_gpt_irq_ops = {
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.map = mpc52xx_gpt_irq_map,
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.xlate = mpc52xx_gpt_irq_xlate,
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};
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static void
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mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
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{
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int cascade_virq;
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unsigned long flags;
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u32 mode;
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cascade_virq = irq_of_parse_and_map(node, 0);
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if (!cascade_virq)
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return;
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gpt->irqhost = irq_domain_add_linear(node, 1, &mpc52xx_gpt_irq_ops, gpt);
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if (!gpt->irqhost) {
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dev_err(gpt->dev, "irq_domain_add_linear() failed\n");
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return;
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}
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irq_set_handler_data(cascade_virq, gpt);
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irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
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/* If the GPT is currently disabled, then change it to be in Input
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* Capture mode. If the mode is non-zero, then the pin could be
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* already in use for something. */
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spin_lock_irqsave(&gpt->lock, flags);
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mode = in_be32(&gpt->regs->mode);
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if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
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out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
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spin_unlock_irqrestore(&gpt->lock, flags);
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dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
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}
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/* ---------------------------------------------------------------------
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* GPIOLIB hooks
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*/
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#if defined(CONFIG_GPIOLIB)
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static inline struct mpc52xx_gpt_priv *gc_to_mpc52xx_gpt(struct gpio_chip *gc)
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{
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return container_of(gc, struct mpc52xx_gpt_priv, gc);
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}
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static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
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return (in_be32(&gpt->regs->status) >> 8) & 1;
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}
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static void
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mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
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{
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struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
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unsigned long flags;
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u32 r;
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dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
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r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
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spin_lock_irqsave(&gpt->lock, flags);
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clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
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spin_unlock_irqrestore(&gpt->lock, flags);
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}
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static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
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unsigned long flags;
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dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
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spin_lock_irqsave(&gpt->lock, flags);
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clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
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spin_unlock_irqrestore(&gpt->lock, flags);
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return 0;
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}
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static int
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mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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mpc52xx_gpt_gpio_set(gc, gpio, val);
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return 0;
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}
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static void
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mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
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{
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int rc;
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/* Only setup GPIO if the device tree claims the GPT is
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* a GPIO controller */
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if (!of_find_property(node, "gpio-controller", NULL))
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return;
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gpt->gc.label = kstrdup(node->full_name, GFP_KERNEL);
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if (!gpt->gc.label) {
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dev_err(gpt->dev, "out of memory\n");
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return;
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}
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gpt->gc.ngpio = 1;
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gpt->gc.direction_input = mpc52xx_gpt_gpio_dir_in;
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gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
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gpt->gc.get = mpc52xx_gpt_gpio_get;
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gpt->gc.set = mpc52xx_gpt_gpio_set;
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gpt->gc.base = -1;
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gpt->gc.of_node = node;
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/* Setup external pin in GPIO mode */
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clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
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MPC52xx_GPT_MODE_MS_GPIO);
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rc = gpiochip_add(&gpt->gc);
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if (rc)
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dev_err(gpt->dev, "gpiochip_add() failed; rc=%i\n", rc);
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dev_dbg(gpt->dev, "%s() complete.\n", __func__);
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}
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#else /* defined(CONFIG_GPIOLIB) */
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static void
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mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { }
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#endif /* defined(CONFIG_GPIOLIB) */
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/***********************************************************************
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* Timer API
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*/
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/**
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* mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
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* @irq: irq of timer.
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*/
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struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq)
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{
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struct mpc52xx_gpt_priv *gpt;
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struct list_head *pos;
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/* Iterate over the list of timers looking for a matching device */
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mutex_lock(&mpc52xx_gpt_list_mutex);
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list_for_each(pos, &mpc52xx_gpt_list) {
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gpt = container_of(pos, struct mpc52xx_gpt_priv, list);
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if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) {
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mutex_unlock(&mpc52xx_gpt_list_mutex);
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return gpt;
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}
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}
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mutex_unlock(&mpc52xx_gpt_list_mutex);
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return NULL;
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}
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EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
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static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,
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int continuous, int as_wdt)
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{
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u32 clear, set;
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u64 clocks;
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u32 prescale;
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unsigned long flags;
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clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS;
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set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
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if (as_wdt) {
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clear |= MPC52xx_GPT_MODE_IRQ_EN;
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set |= MPC52xx_GPT_MODE_WDT_EN;
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} else if (continuous)
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set |= MPC52xx_GPT_MODE_CONTINUOUS;
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/* Determine the number of clocks in the requested period. 64 bit
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* arithmatic is done here to preserve the precision until the value
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* is scaled back down into the u32 range. Period is in 'ns', bus
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* frequency is in Hz. */
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clocks = period * (u64)gpt->ipb_freq;
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do_div(clocks, 1000000000); /* Scale it down to ns range */
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/* This device cannot handle a clock count greater than 32 bits */
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if (clocks > 0xffffffff)
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return -EINVAL;
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/* Calculate the prescaler and count values from the clocks value.
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* 'clocks' is the number of clock ticks in the period. The timer
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* has 16 bit precision and a 16 bit prescaler. Prescaler is
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* calculated by integer dividing the clocks by 0x10000 (shifting
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* down 16 bits) to obtain the smallest possible divisor for clocks
|
|
* to get a 16 bit count value.
|
|
*
|
|
* Note: the prescale register is '1' based, not '0' based. ie. a
|
|
* value of '1' means divide the clock by one. 0xffff divides the
|
|
* clock by 0xffff. '0x0000' does not divide by zero, but wraps
|
|
* around and divides by 0x10000. That is why prescale must be
|
|
* a u32 variable, not a u16, for this calculation. */
|
|
prescale = (clocks >> 16) + 1;
|
|
do_div(clocks, prescale);
|
|
if (clocks > 0xffff) {
|
|
pr_err("calculation error; prescale:%x clocks:%llx\n",
|
|
prescale, clocks);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Set and enable the timer, reject an attempt to use a wdt as gpt */
|
|
spin_lock_irqsave(&gpt->lock, flags);
|
|
if (as_wdt)
|
|
gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
|
|
else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
|
|
spin_unlock_irqrestore(&gpt->lock, flags);
|
|
return -EBUSY;
|
|
}
|
|
out_be32(&gpt->regs->count, prescale << 16 | clocks);
|
|
clrsetbits_be32(&gpt->regs->mode, clear, set);
|
|
spin_unlock_irqrestore(&gpt->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* mpc52xx_gpt_start_timer - Set and enable the GPT timer
|
|
* @gpt: Pointer to gpt private data structure
|
|
* @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
|
|
* @continuous: set to 1 to make timer continuous free running
|
|
*
|
|
* An interrupt will be generated every time the timer fires
|
|
*/
|
|
int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
|
|
int continuous)
|
|
{
|
|
return mpc52xx_gpt_do_start(gpt, period, continuous, 0);
|
|
}
|
|
EXPORT_SYMBOL(mpc52xx_gpt_start_timer);
|
|
|
|
/**
|
|
* mpc52xx_gpt_stop_timer - Stop a gpt
|
|
* @gpt: Pointer to gpt private data structure
|
|
*
|
|
* Returns an error if attempting to stop a wdt
|
|
*/
|
|
int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
|
|
{
|
|
unsigned long flags;
|
|
|
|
/* reject the operation if the timer is used as watchdog (gpt 0 only) */
|
|
spin_lock_irqsave(&gpt->lock, flags);
|
|
if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
|
|
spin_unlock_irqrestore(&gpt->lock, flags);
|
|
return -EBUSY;
|
|
}
|
|
|
|
clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
|
|
spin_unlock_irqrestore(&gpt->lock, flags);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(mpc52xx_gpt_stop_timer);
|
|
|
|
/**
|
|
* mpc52xx_gpt_timer_period - Read the timer period
|
|
* @gpt: Pointer to gpt private data structure
|
|
*
|
|
* Returns the timer period in ns
|
|
*/
|
|
u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)
|
|
{
|
|
u64 period;
|
|
u64 prescale;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&gpt->lock, flags);
|
|
period = in_be32(&gpt->regs->count);
|
|
spin_unlock_irqrestore(&gpt->lock, flags);
|
|
|
|
prescale = period >> 16;
|
|
period &= 0xffff;
|
|
if (prescale == 0)
|
|
prescale = 0x10000;
|
|
period = period * prescale * 1000000000ULL;
|
|
do_div(period, (u64)gpt->ipb_freq);
|
|
return period;
|
|
}
|
|
EXPORT_SYMBOL(mpc52xx_gpt_timer_period);
|
|
|
|
#if defined(CONFIG_MPC5200_WDT)
|
|
/***********************************************************************
|
|
* Watchdog API for gpt0
|
|
*/
|
|
|
|
#define WDT_IDENTITY "mpc52xx watchdog on GPT0"
|
|
|
|
/* wdt_is_active stores whether or not the /dev/watchdog device is opened */
|
|
static unsigned long wdt_is_active;
|
|
|
|
/* wdt-capable gpt */
|
|
static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt;
|
|
|
|
/* low-level wdt functions */
|
|
static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt)
|
|
{
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&gpt_wdt->lock, flags);
|
|
out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING);
|
|
spin_unlock_irqrestore(&gpt_wdt->lock, flags);
|
|
}
|
|
|
|
/* wdt misc device api */
|
|
static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data,
|
|
size_t len, loff_t *ppos)
|
|
{
|
|
struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
|
|
mpc52xx_gpt_wdt_ping(gpt_wdt);
|
|
return 0;
|
|
}
|
|
|
|
static const struct watchdog_info mpc5200_wdt_info = {
|
|
.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
|
|
.identity = WDT_IDENTITY,
|
|
};
|
|
|
|
static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd,
|
|
unsigned long arg)
|
|
{
|
|
struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
|
|
int __user *data = (int __user *)arg;
|
|
int timeout;
|
|
u64 real_timeout;
|
|
int ret = 0;
|
|
|
|
switch (cmd) {
|
|
case WDIOC_GETSUPPORT:
|
|
ret = copy_to_user(data, &mpc5200_wdt_info,
|
|
sizeof(mpc5200_wdt_info));
|
|
if (ret)
|
|
ret = -EFAULT;
|
|
break;
|
|
|
|
case WDIOC_GETSTATUS:
|
|
case WDIOC_GETBOOTSTATUS:
|
|
ret = put_user(0, data);
|
|
break;
|
|
|
|
case WDIOC_KEEPALIVE:
|
|
mpc52xx_gpt_wdt_ping(gpt_wdt);
|
|
break;
|
|
|
|
case WDIOC_SETTIMEOUT:
|
|
ret = get_user(timeout, data);
|
|
if (ret)
|
|
break;
|
|
real_timeout = (u64) timeout * 1000000000ULL;
|
|
ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1);
|
|
if (ret)
|
|
break;
|
|
/* fall through and return the timeout */
|
|
|
|
case WDIOC_GETTIMEOUT:
|
|
/* we need to round here as to avoid e.g. the following
|
|
* situation:
|
|
* - timeout requested is 1 second;
|
|
* - real timeout @33MHz is 999997090ns
|
|
* - the int divide by 10^9 will return 0.
|
|
*/
|
|
real_timeout =
|
|
mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL;
|
|
do_div(real_timeout, 1000000000ULL);
|
|
timeout = (int) real_timeout;
|
|
ret = put_user(timeout, data);
|
|
break;
|
|
|
|
default:
|
|
ret = -ENOTTY;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int mpc52xx_wdt_open(struct inode *inode, struct file *file)
|
|
{
|
|
int ret;
|
|
|
|
/* sanity check */
|
|
if (!mpc52xx_gpt_wdt)
|
|
return -ENODEV;
|
|
|
|
/* /dev/watchdog can only be opened once */
|
|
if (test_and_set_bit(0, &wdt_is_active))
|
|
return -EBUSY;
|
|
|
|
/* Set and activate the watchdog with 30 seconds timeout */
|
|
ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL,
|
|
0, 1);
|
|
if (ret) {
|
|
clear_bit(0, &wdt_is_active);
|
|
return ret;
|
|
}
|
|
|
|
file->private_data = mpc52xx_gpt_wdt;
|
|
return nonseekable_open(inode, file);
|
|
}
|
|
|
|
static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
|
|
{
|
|
/* note: releasing the wdt in NOWAYOUT-mode does not stop it */
|
|
#if !defined(CONFIG_WATCHDOG_NOWAYOUT)
|
|
struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&gpt_wdt->lock, flags);
|
|
clrbits32(&gpt_wdt->regs->mode,
|
|
MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
|
|
gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
|
|
spin_unlock_irqrestore(&gpt_wdt->lock, flags);
|
|
#endif
|
|
clear_bit(0, &wdt_is_active);
|
|
return 0;
|
|
}
|
|
|
|
|
|
static const struct file_operations mpc52xx_wdt_fops = {
|
|
.owner = THIS_MODULE,
|
|
.llseek = no_llseek,
|
|
.write = mpc52xx_wdt_write,
|
|
.unlocked_ioctl = mpc52xx_wdt_ioctl,
|
|
.open = mpc52xx_wdt_open,
|
|
.release = mpc52xx_wdt_release,
|
|
};
|
|
|
|
static struct miscdevice mpc52xx_wdt_miscdev = {
|
|
.minor = WATCHDOG_MINOR,
|
|
.name = "watchdog",
|
|
.fops = &mpc52xx_wdt_fops,
|
|
};
|
|
|
|
static int mpc52xx_gpt_wdt_init(void)
|
|
{
|
|
int err;
|
|
|
|
/* try to register the watchdog misc device */
|
|
err = misc_register(&mpc52xx_wdt_miscdev);
|
|
if (err)
|
|
pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY);
|
|
else
|
|
pr_info("%s: watchdog device registered\n", WDT_IDENTITY);
|
|
return err;
|
|
}
|
|
|
|
static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
|
|
const u32 *period)
|
|
{
|
|
u64 real_timeout;
|
|
|
|
/* remember the gpt for the wdt operation */
|
|
mpc52xx_gpt_wdt = gpt;
|
|
|
|
/* configure the wdt if the device tree contained a timeout */
|
|
if (!period || *period == 0)
|
|
return 0;
|
|
|
|
real_timeout = (u64) *period * 1000000000ULL;
|
|
if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1))
|
|
dev_warn(gpt->dev, "starting as wdt failed\n");
|
|
else
|
|
dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
|
|
static int mpc52xx_gpt_wdt_init(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
|
|
const u32 *period)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CONFIG_MPC5200_WDT */
|
|
|
|
/* ---------------------------------------------------------------------
|
|
* of_platform bus binding code
|
|
*/
|
|
static int mpc52xx_gpt_probe(struct platform_device *ofdev)
|
|
{
|
|
struct mpc52xx_gpt_priv *gpt;
|
|
|
|
gpt = kzalloc(sizeof *gpt, GFP_KERNEL);
|
|
if (!gpt)
|
|
return -ENOMEM;
|
|
|
|
spin_lock_init(&gpt->lock);
|
|
gpt->dev = &ofdev->dev;
|
|
gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
|
|
gpt->regs = of_iomap(ofdev->dev.of_node, 0);
|
|
if (!gpt->regs) {
|
|
kfree(gpt);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
dev_set_drvdata(&ofdev->dev, gpt);
|
|
|
|
mpc52xx_gpt_gpio_setup(gpt, ofdev->dev.of_node);
|
|
mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node);
|
|
|
|
mutex_lock(&mpc52xx_gpt_list_mutex);
|
|
list_add(&gpt->list, &mpc52xx_gpt_list);
|
|
mutex_unlock(&mpc52xx_gpt_list_mutex);
|
|
|
|
/* check if this device could be a watchdog */
|
|
if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) ||
|
|
of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) {
|
|
const u32 *on_boot_wdt;
|
|
|
|
gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
|
|
on_boot_wdt = of_get_property(ofdev->dev.of_node,
|
|
"fsl,wdt-on-boot", NULL);
|
|
if (on_boot_wdt) {
|
|
dev_info(gpt->dev, "used as watchdog\n");
|
|
gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
|
|
} else
|
|
dev_info(gpt->dev, "can function as watchdog\n");
|
|
mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mpc52xx_gpt_remove(struct platform_device *ofdev)
|
|
{
|
|
return -EBUSY;
|
|
}
|
|
|
|
static const struct of_device_id mpc52xx_gpt_match[] = {
|
|
{ .compatible = "fsl,mpc5200-gpt", },
|
|
|
|
/* Depreciated compatible values; don't use for new dts files */
|
|
{ .compatible = "fsl,mpc5200-gpt-gpio", },
|
|
{ .compatible = "mpc5200-gpt", },
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver mpc52xx_gpt_driver = {
|
|
.driver = {
|
|
.name = "mpc52xx-gpt",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = mpc52xx_gpt_match,
|
|
},
|
|
.probe = mpc52xx_gpt_probe,
|
|
.remove = mpc52xx_gpt_remove,
|
|
};
|
|
|
|
static int __init mpc52xx_gpt_init(void)
|
|
{
|
|
return platform_driver_register(&mpc52xx_gpt_driver);
|
|
}
|
|
|
|
/* Make sure GPIOs and IRQs get set up before anyone tries to use them */
|
|
subsys_initcall(mpc52xx_gpt_init);
|
|
device_initcall(mpc52xx_gpt_wdt_init);
|