Abhinav Kumar 8531f0587f drm/msm/dsi: configure VCO rate for 10nm PLL driver ... Currenty the VCO rate in the 10nm PLL driver relies on the parent rate which is not configured. Configure the VCO rate to 19.2 Mhz as required by the 10nm PLL driver. Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>		2018-11-30 11:57:53 -05:00
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dsi_pll_10nm.c	drm/msm/dsi: configure VCO rate for 10nm PLL driver	2018-11-30 11:57:53 -05:00
dsi_pll_14nm.c	clk: divider: fix incorrect usage of container_of	2017-12-28 15:16:04 -08:00
dsi_pll_28nm_8960.c	drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocks	2016-11-02 10:48:09 -04:00
dsi_pll_28nm.c	drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocks	2016-11-02 10:48:09 -04:00
dsi_pll.c	drm/msm/dsi: Add skeleton 10nm PHY/PLL code	2018-02-20 10:41:20 -05:00
dsi_pll.h	drm/msm/dsi: Add skeleton 10nm PHY/PLL code	2018-02-20 10:41:20 -05:00