Eric Yang e15fc81f11 drm/amd/display: clean up encoding checks ... [Why] All ASICS we support has YCbCr support, so the check is unnecessary, the currently logic in validate output also returns true all the time, so the unneccessary logic is removed Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2018-10-09 17:02:15 -05:00
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hw	drm/amd/display: clean up encoding checks	2018-10-09 17:02:15 -05:00
bw_fixed.h	amdgpu/dc: allow inlining constant int to fixed a lot better.	2017-09-29 13:03:35 -04:00
clock_source.h	drm/amd/display: remove unused clk_src code	2018-09-10 22:42:55 -05:00
compressor.h	drm/amd/display: Initial prototype of FBC implementation	2017-09-26 18:15:56 -04:00
core_status.h	drm/amd/display: Add timing validation against dongle cap	2017-11-28 17:54:16 -05:00
core_types.h	drm/amd/display: Calculate swizzle mode using bpp during validation	2018-10-09 17:01:55 -05:00
custom_float.h	drm/amd/display: Enable regamma 25 segments and use double buffer.	2017-09-26 17:14:18 -04:00
dc_link_ddc.h	drm/amd/display: Return aux replies directly to DRM	2018-07-13 14:48:36 -05:00
dc_link_dp.h	drm/amd/display: Retry link training again	2018-07-27 09:07:42 -05:00
dce_calcs.h	drm/amdgpu/display: remove VEGAM config option	2018-05-18 16:08:18 -05:00
dcn_calcs.h	drm/amd/display: program v_update and v_ready with proper field	2018-09-26 21:09:06 -05:00
hw_sequencer.h	drm/amd/display: Support reading hw state from debugfs file	2018-08-27 15:20:49 -05:00
link_hwss.h	drm/amd/display: add eDP 1.2+ polling for T7	2018-02-19 14:19:34 -05:00
reg_helper.h	drm/amd/display: generic indirect register access	2018-07-13 14:47:33 -05:00
resource.h	drm/amd/display: Calculate swizzle mode using bpp during validation	2018-10-09 17:01:55 -05:00