forked from Minki/linux
7a2bd1cc39
OMAP2420 and OMAP2430 chips each have two on-chip APLLs. When locked, one APLL generates a 96 MHz rate; the other, a 54 MHz rate. Previously we treated these clocks as fixed-rate clocks at the locked rates, but this isn't quite right. The locked rate should be returned when the APLL is locked, and a zero rate should be returned when the APLL is stopped. This patch adds the infrastructure that will be used by the CCF changes. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Mike Turquette <mturquette@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
81 lines
2.7 KiB
C
81 lines
2.7 KiB
C
/*
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* OMAP2 clock function prototypes and macros
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*
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* Copyright (C) 2005-2010 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
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#ifdef CONFIG_COMMON_CLK
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#include <linux/clk-provider.h>
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#include "clock.h"
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unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
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unsigned long parent_rate);
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int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate);
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unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
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unsigned long parent_rate);
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unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
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unsigned long parent_rate);
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unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
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unsigned long parent_rate);
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void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
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unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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#else
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unsigned long omap2_table_mpu_recalc(struct clk *clk);
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int omap2_select_table_rate(struct clk *clk, unsigned long rate);
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long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
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unsigned long omap2xxx_sys_clk_recalc(struct clk *clk);
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unsigned long omap2_osc_clk_recalc(struct clk *clk);
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unsigned long omap2_dpllcore_recalc(struct clk *clk);
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int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
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void omap2xxx_clkt_dpllcore_init(struct clk *clk);
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#endif
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unsigned long omap2xxx_clk_get_core_rate(void);
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u32 omap2xxx_get_apll_clkin(void);
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u32 omap2xxx_get_sysclkdiv(void);
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void omap2xxx_clk_prepare_for_reboot(void);
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void omap2xxx_clkt_vps_check_bootloader_rates(void);
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void omap2xxx_clkt_vps_late_init(void);
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#ifdef CONFIG_SOC_OMAP2420
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int omap2420_clk_init(void);
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#else
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#define omap2420_clk_init() do { } while(0)
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#endif
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#ifdef CONFIG_SOC_OMAP2430
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int omap2430_clk_init(void);
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#else
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#define omap2430_clk_init() do { } while(0)
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#endif
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extern void __iomem *prcm_clksrc_ctrl;
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#ifdef CONFIG_COMMON_CLK
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extern struct clk_hw *dclk_hw;
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int omap2_enable_osc_ck(struct clk_hw *hw);
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void omap2_disable_osc_ck(struct clk_hw *hw);
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int omap2_clk_apll96_enable(struct clk_hw *hw);
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int omap2_clk_apll54_enable(struct clk_hw *hw);
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void omap2_clk_apll96_disable(struct clk_hw *hw);
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void omap2_clk_apll54_disable(struct clk_hw *hw);
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#else
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extern const struct clkops clkops_omap2430_i2chs_wait;
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extern const struct clkops clkops_oscck;
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extern const struct clkops clkops_apll96;
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extern const struct clkops clkops_apll54;
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#endif
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#endif
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