Shawn Lin 7a03fe6f48 clk: rockchip: reset init state before mmc card initialization ... mmc host controller's IO input/output timing is unpredictable if bootloader execute tuning for HS200 mode. It might make kernel failed to initialize mmc card in identification mode. The root cause is tuning phase and degree setting for HS200 mode in bootloader aren't applicable to that of identification mode in kernel stage. Anyway, we can't force all bootloaders to reset tuning phase and degree setting before into kernel. Simply reset it in rockchip_clk_register_mmc. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2015-10-01 16:36:54 -07:00
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clk-cpu.c	clk: rockchip: Properly include clk.h	2015-07-20 11:11:10 -07:00
clk-inverter.c	clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)	2015-08-24 16:49:12 -07:00
clk-mmc-phase.c	clk: rockchip: reset init state before mmc card initialization	2015-10-01 16:36:54 -07:00
clk-pll.c	clk: rockchip: don't use clk_ APIs in the pll init-callback	2015-10-01 14:58:28 -07:00
clk-rk3188.c	clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188	2015-09-10 13:55:30 -07:00
clk-rk3288.c	This is the bulk of pin control changes for the v4.3 development	2015-09-04 10:22:09 -07:00
clk-rk3368.c	clk: rockchip: add critical clock for rk3368	2015-09-14 12:49:39 -07:00
clk-rockchip.c	clk: rockchip: fix function type for CLK_OF_DECLARE	2014-05-20 14:25:22 -05:00
clk.c	clk: rockchip: add support for phase inverters	2015-07-06 15:04:40 -07:00
clk.h	clk: rockchip: Fix PLL bandwidth	2015-07-28 11:59:12 -07:00
Makefile	clk: rockchip: add rk3368 clock controller	2015-07-06 15:09:22 -07:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00