f3354ab674
When both 'cache-size' and 'cache-sets' are specified for a L2 cache
controller node, parse those properties and set up the
set size based on which type of L2 cache controller we are using.
Update the L2 cache controller Device Tree binding with the optional
'cache-size', 'cache-sets', 'cache-block-size' and 'cache-line-size'
properties. These come from the ePAPR specification.
Using the cache size, number of sets and cache line size we can
calculate desired associativity of the L2 cache. This is done
by the calculation:
set size = cache size / sets
ways = set size / line size
way size = cache size / ways = sets * line size
associativity = cache size / way size
Example output from the PB1176 DT that look like this:
L2: l2-cache {
compatible = "arm,l220-cache";
(...)
arm,override-auxreg;
cache-size = <131072>; // 128kB
cache-sets = <512>;
cache-line-size = <32>;
};
Ends up like this:
L2C OF: override cache size: 131072 bytes (128KB)
L2C OF: override line size: 32 bytes
L2C OF: override way size: 16384 bytes (16KB)
L2C OF: override associativity: 8
L2C: DT/platform modifies aux control register: 0x02020fff -> 0x02030fff
L2C-220 cache controller enabled, 8 ways, 128 kB
L2C-220: CACHE_ID 0x41000486, AUX_CTRL 0x06030fff
Which is consistent with the value earlier hardcoded for the
PB1176 platform.
This patch is an extended version based on the initial patch
by Florian Fainelli.
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
73 lines
3.2 KiB
Plaintext
73 lines
3.2 KiB
Plaintext
* ARM L2 Cache Controller
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ARM cores often have a separate level 2 cache controller. There are various
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implementations of the L2 cache controller with compatible programming models.
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Some of the properties that are just prefixed "cache-*" are taken from section
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3.7.3 of the ePAPR v1.1 specification which can be found at:
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https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
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The ARM L2 cache representation in the device tree should be done as follows:
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Required properties:
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- compatible : should be one of:
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"arm,pl310-cache"
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"arm,l220-cache"
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"arm,l210-cache"
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"bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
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"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
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offset needs to be added to the address before passing down to the L2
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cache controller
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"marvell,aurora-system-cache": Marvell Controller designed to be
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compatible with the ARM one, with system cache mode (meaning
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maintenance operations on L1 are broadcasted to the L2 and L2
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performs the same operation).
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"marvell,aurora-outer-cache": Marvell Controller designed to be
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compatible with the ARM one with outer cache mode.
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"marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
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with arm,pl310-cache controller.
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- cache-unified : Specifies the cache is a unified cache.
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- cache-level : Should be set to 2 for a level 2 cache.
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- reg : Physical base address and size of cache controller's memory mapped
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registers.
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Optional properties:
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- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
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read, write and setup latencies. Minimum valid values are 1. Controllers
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without setup latency control should use a value of 0.
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- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
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read, write and setup latencies. Controllers without setup latency control
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should use 0. Controllers without separate read and write Tag RAM latency
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values should only use the first cell.
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- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
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- arm,filter-ranges : <start length> Starting address and length of window to
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filter. Addresses in the filter window are directed to the M1 port. Other
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addresses will go to the M0 port.
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- arm,io-coherent : indicates that the system is operating in an hardware
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I/O coherent mode. Valid only when the arm,pl310-cache compatible
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string is used.
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- interrupts : 1 combined interrupt.
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- cache-size : specifies the size in bytes of the cache
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- cache-sets : specifies the number of associativity sets of the cache
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- cache-block-size : specifies the size in bytes of a cache block
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- cache-line-size : specifies the size in bytes of a line in the cache,
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if this is not specified, the line size is assumed to be equal to the
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cache block size
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- cache-id-part: cache id part number to be used if it is not present
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on hardware
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- wt-override: If present then L2 is forced to Write through mode
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Example:
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L2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0xfff12000 0x1000>;
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arm,data-latency = <1 1 1>;
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arm,tag-latency = <2 2 2>;
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arm,filter-ranges = <0x80000000 0x8000000>;
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cache-unified;
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cache-level = <2>;
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interrupts = <45>;
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};
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