forked from Minki/linux
796c2b35a4
This board is based on Juno r0 with updated Cortex A5x revisions and board errata fixes. It also contains coherent ThinLinks ports on the expansion slot that allow for an AXI master on the daughter card to participate in a coherency domain. Support for SoC PCIe host bridge will be added as a separate series. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Acked-by: Jon Medhurst <tixy@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com>
117 lines
2.2 KiB
Plaintext
117 lines
2.2 KiB
Plaintext
/*
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* ARM Ltd. Juno Platform
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*
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* Copyright (c) 2015 ARM Ltd.
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*
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* This file is licensed under a dual GPLv2 or BSD license.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "ARM Juno development board (r1)";
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compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &soc_uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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A57_0: cpu@0 {
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A57_L2>;
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};
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A57_1: cpu@1 {
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compatible = "arm,cortex-a57","arm,armv8";
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reg = <0x0 0x1>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A57_L2>;
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};
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A53_0: cpu@100 {
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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};
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A53_1: cpu@101 {
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x101>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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};
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A53_2: cpu@102 {
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x102>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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};
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A53_3: cpu@103 {
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compatible = "arm,cortex-a53","arm,armv8";
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reg = <0x0 0x103>;
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device_type = "cpu";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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};
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A57_L2: l2-cache0 {
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compatible = "cache";
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};
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A53_L2: l2-cache1 {
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compatible = "cache";
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&A57_0>,
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<&A57_1>,
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<&A53_0>,
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<&A53_1>,
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<&A53_2>,
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<&A53_3>;
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};
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#include "juno-base.dtsi"
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};
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&memtimer {
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status = "okay";
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};
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