1b1f42d8fd
This moves and renames the AMDGPU scheduler to a common location in DRM in order to facilitate re-use by other drivers. This is mostly a straight forward rename with no code changes. One notable exception is the function to_drm_sched_fence(), which is no longer a inline header function to avoid the need to export the drm_sched_fence_ops_scheduled and drm_sched_fence_ops_finished structures. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
78 lines
2.9 KiB
C
78 lines
2.9 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_VCN_H__
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#define __AMDGPU_VCN_H__
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#define AMDGPU_VCN_STACK_SIZE (200*1024)
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#define AMDGPU_VCN_HEAP_SIZE (256*1024)
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#define AMDGPU_VCN_SESSION_SIZE (50*1024)
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#define AMDGPU_VCN_FIRMWARE_OFFSET 256
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#define AMDGPU_VCN_MAX_ENC_RINGS 3
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#define VCN_DEC_CMD_FENCE 0x00000000
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#define VCN_DEC_CMD_TRAP 0x00000001
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#define VCN_DEC_CMD_WRITE_REG 0x00000004
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#define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006
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#define VCN_DEC_CMD_PACKET_START 0x0000000a
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#define VCN_DEC_CMD_PACKET_END 0x0000000b
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#define VCN_ENC_CMD_NO_OP 0x00000000
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#define VCN_ENC_CMD_END 0x00000001
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#define VCN_ENC_CMD_IB 0x00000002
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#define VCN_ENC_CMD_FENCE 0x00000003
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#define VCN_ENC_CMD_TRAP 0x00000004
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#define VCN_ENC_CMD_REG_WRITE 0x0000000b
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#define VCN_ENC_CMD_REG_WAIT 0x0000000c
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struct amdgpu_vcn {
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struct amdgpu_bo *vcpu_bo;
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void *cpu_addr;
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uint64_t gpu_addr;
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unsigned fw_version;
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void *saved_bo;
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struct delayed_work idle_work;
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const struct firmware *fw; /* VCN firmware */
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struct amdgpu_ring ring_dec;
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struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
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struct amdgpu_irq_src irq;
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struct drm_sched_entity entity_dec;
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struct drm_sched_entity entity_enc;
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unsigned num_enc_rings;
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};
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int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
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int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
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int amdgpu_vcn_suspend(struct amdgpu_device *adev);
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int amdgpu_vcn_resume(struct amdgpu_device *adev);
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void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
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void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
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int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
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int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
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int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
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int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
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#endif
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