forked from Minki/linux
e00c5498a2
1. PCI and reset are factored out into pq2.c. I renamed them from m82xx to pq2 because they won't work on the Integrated Host Processor line of 82xx chips (i.e. 8240, 8245, and such). 2. The PCI PIC, which is nominally board-specific, is used on multiple boards, and thus is used into pq2ads-pci-pic.c. 3. The new CPM binding is used. 4. General cleanup. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
83 lines
1.9 KiB
C
83 lines
1.9 KiB
C
/*
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* Common PowerQUICC II code.
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*
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* Author: Scott Wood <scottwood@freescale.com>
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* Copyright (c) 2007 Freescale Semiconductor
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*
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* Based on code by Vitaly Bordug <vbordug@ru.mvista.com>
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* pq2_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
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* Copyright (c) 2006 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <asm/cpm2.h>
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#include <asm/io.h>
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#include <asm/pci-bridge.h>
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#include <asm/system.h>
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#include <platforms/82xx/pq2.h>
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#define RMR_CSRE 0x00000001
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void pq2_restart(char *cmd)
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{
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local_irq_disable();
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setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE);
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/* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
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mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
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in_8(&cpm2_immr->im_clkrst.res[0]);
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panic("Restart failed\n");
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}
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#ifdef CONFIG_PCI
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static int pq2_pci_exclude_device(struct pci_controller *hose,
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u_char bus, u8 devfn)
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{
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if (bus == 0 && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return PCIBIOS_SUCCESSFUL;
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}
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static void __init pq2_pci_add_bridge(struct device_node *np)
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{
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struct pci_controller *hose;
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struct resource r;
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if (of_address_to_resource(np, 0, &r) || r.end - r.start < 0x10b)
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goto err;
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pci_assign_all_buses = 1;
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hose = pcibios_alloc_controller(np);
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if (!hose)
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return;
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hose->arch_data = np;
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setup_indirect_pci(hose, r.start + 0x100, r.start + 0x104, 0);
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pci_process_bridge_OF_ranges(hose, np, 1);
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return;
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err:
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printk(KERN_ERR "No valid PCI reg property in device tree\n");
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}
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void __init pq2_init_pci(void)
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{
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struct device_node *np = NULL;
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ppc_md.pci_exclude_device = pq2_pci_exclude_device;
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while ((np = of_find_compatible_node(np, NULL, "fsl,pq2-pci")))
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pq2_pci_add_bridge(np);
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}
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#endif
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