78a714aba0
Since GICv3 supports much more than the 8 CPUs the GICv2 ITARGETSR register can handle, the new IROUTER register covers the whole range of possible target (V)CPUs by using the same MPIDR that the cores report themselves. In addition to translating this MPIDR into a vcpu pointer we store the originally written value as well. The architecture allows to write any values into the register, which must be read back as written. Since we don't support affinity level 3, we don't need to take care about the upper word of this 64-bit register, which simplifies the handling a bit. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> |
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| .. | ||
| hyp | ||
| vgic | ||
| arch_timer.c | ||
| pmu.c | ||
| trace.h | ||
| vgic-v2-emul.c | ||
| vgic-v2.c | ||
| vgic-v3-emul.c | ||
| vgic-v3.c | ||
| vgic.c | ||
| vgic.h | ||