forked from Minki/linux
efcac6589a
The DSCR (aka Data Stream Control Register) is supported on some server PowerPC chips and allow some control over the prefetch of data streams. This patch allows the value to be specified per thread by emulating the corresponding mfspr and mtspr instructions. Children of such threads inherit the value. Other threads use a default value that can be specified in sysfs - /sys/devices/system/cpu/dscr_default. If a thread starts with non default value in the sysfs entry, all children threads inherit this non default value even if the sysfs value is changed later. Signed-off-by: Alexey Kardashevskiy <aik@au1.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
165 lines
6.3 KiB
C
165 lines
6.3 KiB
C
/*
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* Copyright 2009 Freescale Semicondutor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* provides masks and opcode images for use by code generation, emulation
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* and for instructions that older assemblers might not know about
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*/
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#ifndef _ASM_POWERPC_PPC_OPCODE_H
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#define _ASM_POWERPC_PPC_OPCODE_H
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#include <linux/stringify.h>
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#include <asm/asm-compat.h>
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/* sorted alphabetically */
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#define PPC_INST_DCBA 0x7c0005ec
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#define PPC_INST_DCBA_MASK 0xfc0007fe
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#define PPC_INST_DCBAL 0x7c2005ec
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#define PPC_INST_DCBZL 0x7c2007ec
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#define PPC_INST_ISEL 0x7c00001e
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#define PPC_INST_ISEL_MASK 0xfc00003e
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#define PPC_INST_LDARX 0x7c0000a8
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#define PPC_INST_LSWI 0x7c0004aa
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#define PPC_INST_LSWX 0x7c00042a
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#define PPC_INST_LWARX 0x7c000028
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#define PPC_INST_LWSYNC 0x7c2004ac
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#define PPC_INST_LXVD2X 0x7c000698
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#define PPC_INST_MCRXR 0x7c000400
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#define PPC_INST_MCRXR_MASK 0xfc0007fe
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#define PPC_INST_MFSPR_PVR 0x7c1f42a6
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#define PPC_INST_MFSPR_PVR_MASK 0xfc1fffff
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#define PPC_INST_MSGSND 0x7c00019c
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#define PPC_INST_NOP 0x60000000
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#define PPC_INST_POPCNTB 0x7c0000f4
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#define PPC_INST_POPCNTB_MASK 0xfc0007fe
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#define PPC_INST_POPCNTD 0x7c0003f4
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#define PPC_INST_POPCNTW 0x7c0002f4
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#define PPC_INST_RFCI 0x4c000066
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#define PPC_INST_RFDI 0x4c00004e
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#define PPC_INST_RFMCI 0x4c00004c
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#define PPC_INST_MFSPR_DSCR 0x7c1102a6
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#define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff
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#define PPC_INST_MTSPR_DSCR 0x7c1103a6
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#define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff
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#define PPC_INST_STRING 0x7c00042a
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#define PPC_INST_STRING_MASK 0xfc0007fe
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#define PPC_INST_STRING_GEN_MASK 0xfc00067e
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#define PPC_INST_STSWI 0x7c0005aa
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#define PPC_INST_STSWX 0x7c00052a
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#define PPC_INST_STXVD2X 0x7c000798
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#define PPC_INST_TLBIE 0x7c000264
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#define PPC_INST_TLBILX 0x7c000024
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#define PPC_INST_WAIT 0x7c00007c
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#define PPC_INST_TLBIVAX 0x7c000624
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#define PPC_INST_TLBSRX_DOT 0x7c0006a5
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#define PPC_INST_XXLOR 0xf0000510
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#define PPC_INST_NAP 0x4c000364
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#define PPC_INST_SLEEP 0x4c0003a4
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/* A2 specific instructions */
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#define PPC_INST_ERATWE 0x7c0001a6
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#define PPC_INST_ERATRE 0x7c000166
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#define PPC_INST_ERATILX 0x7c000066
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#define PPC_INST_ERATIVAX 0x7c000666
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#define PPC_INST_ERATSX 0x7c000126
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#define PPC_INST_ERATSX_DOT 0x7c000127
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/* macros to insert fields into opcodes */
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#define __PPC_RA(a) (((a) & 0x1f) << 16)
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#define __PPC_RB(b) (((b) & 0x1f) << 11)
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#define __PPC_RS(s) (((s) & 0x1f) << 21)
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#define __PPC_RT(s) __PPC_RS(s)
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#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
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#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
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#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
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#define __PPC_XT(s) __PPC_XS(s)
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#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
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#define __PPC_WC(w) (((w) & 0x3) << 21)
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#define __PPC_WS(w) (((w) & 0x1f) << 11)
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/*
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* Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
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* larx with EH set as an illegal instruction.
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*/
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#ifdef CONFIG_PPC64
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#define __PPC_EH(eh) (((eh) & 0x1) << 0)
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#else
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#define __PPC_EH(eh) 0
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#endif
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/* Deal with instructions that older assemblers aren't aware of */
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#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \
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__PPC_RA(a) | __PPC_RB(b))
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#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
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__PPC_RA(a) | __PPC_RB(b))
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#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
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__PPC_RT(t) | __PPC_RA(a) | \
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__PPC_RB(b) | __PPC_EH(eh))
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#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
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__PPC_RT(t) | __PPC_RA(a) | \
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__PPC_RB(b) | __PPC_EH(eh))
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#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
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__PPC_RB(b))
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#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
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__PPC_RA(a) | __PPC_RS(s))
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#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
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__PPC_RA(a) | __PPC_RS(s))
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#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \
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__PPC_RA(a) | __PPC_RS(s))
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#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
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#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
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#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
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#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
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__PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b))
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#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
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#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
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#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
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#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
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__PPC_WC(w))
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#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
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__PPC_RB(a) | __PPC_RS(lp))
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#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
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__PPC_RA(a) | __PPC_RB(b))
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#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
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__PPC_RA(a) | __PPC_RB(b))
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#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
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__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
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#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
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__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
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#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
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__PPC_T_TLB(t) | __PPC_RA(a) | \
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__PPC_RB(b))
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#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
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__PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
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#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
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__PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
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#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
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__PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
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/*
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* Define what the VSX XX1 form instructions will look like, then add
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* the 128 bit load store instructions based on that.
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*/
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#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
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#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
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#define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \
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VSX_XX1((s), (a), (b)))
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#define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \
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VSX_XX1((s), (a), (b)))
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#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
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VSX_XX3((t), (a), (b)))
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#define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
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#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
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#endif /* _ASM_POWERPC_PPC_OPCODE_H */
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