forked from Minki/linux
54a19b4d3f
There are some ABI documents that, while they don't generate any warnings, they have issues when parsed by get_abi.pl script on its output result. Address them, in order to provide a clean output. Reviewed-by: Tom Rix <trix@redhat.com> # for fpga-manager Reviewed-By: Kajol Jain<kjain@linux.ibm.com> # for sysfs-bus-event_source-devices-hv_gpci and sysfs-bus-event_source-devices-hv_24x7 Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> #for IIO Acked-by: Oded Gabbay <oded.gabbay@gmail.com> # for Habanalabs Acked-by: Vaibhav Jain <vaibhav@linux.ibm.com> # for sysfs-bus-papr-pmem Acked-by: Cezary Rojewski <cezary.rojewski@intel.com> # for catpt Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Acked-by: Ilya Dryomov <idryomov@gmail.com> # for rbd Acked-by: Jonathan Corbet <corbet@lwn.net> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/5bc78e5b68ed1e9e39135173857cb2e753be868f.1604042072.git.mchehab+huawei@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
32 lines
1.2 KiB
Plaintext
32 lines
1.2 KiB
Plaintext
What: /sys/bus/iio/devices/iio:deviceX/pll2_feedback_clk_present
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What: /sys/bus/iio/devices/iio:deviceX/pll2_reference_clk_present
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What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_a_present
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What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_b_present
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What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_test_present
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What: /sys/bus/iio/devices/iio:deviceX/vcxo_clk_present
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KernelVersion: 3.4.0
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Contact: linux-iio@vger.kernel.org
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Description:
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Reading returns either '1' or '0'.
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'1' means that the clock in question is present.
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'0' means that the clock is missing.
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What: /sys/bus/iio/devices/iio:deviceX/pllY_locked
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KernelVersion: 3.4.0
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Contact: linux-iio@vger.kernel.org
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Description:
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Reading returns either '1' or '0'. '1' means that the
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pllY is locked.
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What: /sys/bus/iio/devices/iio:deviceX/sync_dividers
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KernelVersion: 3.4.0
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Contact: linux-iio@vger.kernel.org
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Description:
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Writing '1' triggers the clock distribution synchronization
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functionality. All dividers are reset and the channels start
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with their predefined phase offsets (out_altvoltageY_phase).
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Writing this file has the effect as driving the external
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/SYNC pin low.
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