forked from Minki/linux
7737b20b9e
Correct a cache coherency regression introduced with be1664c4 [Another round of fixes for the fp emulator.] for the emulation frame used in delay-slot emulation. Two instructions are copied into the frame and as from the commit referred a cache synchronisation call is made for the second instruction aka `badinst' of the two only. The `flush_cache_sigtramp' interface is reused that guarantees that synchronisation will be made for 8 bytes or 2 instructions starting from the address requested, although if cache lines are wider then a larger area may be synchronised. Change the call to point to the first of the two instructions aka `emul' instead, removing unpredictable behaviour resulting from cache incoherency. This bug only ever manifested itself on systems implementing 4-byte cache lines, typically MIPS I systems, causing all kinds of weirdness. This is because the sequence of two instructions starting from `emul' is 8-byte aligned and for 8-byte or wider cache lines the line synchronised will span both, so the vast majority of systems have escaped unharmed. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9698/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
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| .. | ||
| cp1emu.c | ||
| dp_add.c | ||
| dp_cmp.c | ||
| dp_div.c | ||
| dp_fint.c | ||
| dp_flong.c | ||
| dp_fsp.c | ||
| dp_mul.c | ||
| dp_simple.c | ||
| dp_sqrt.c | ||
| dp_sub.c | ||
| dp_tint.c | ||
| dp_tlong.c | ||
| dsemul.c | ||
| ieee754.c | ||
| ieee754.h | ||
| ieee754d.c | ||
| ieee754dp.c | ||
| ieee754dp.h | ||
| ieee754int.h | ||
| ieee754sp.c | ||
| ieee754sp.h | ||
| Makefile | ||
| me-debugfs.c | ||
| sp_add.c | ||
| sp_cmp.c | ||
| sp_div.c | ||
| sp_fdp.c | ||
| sp_fint.c | ||
| sp_flong.c | ||
| sp_mul.c | ||
| sp_simple.c | ||
| sp_sqrt.c | ||
| sp_sub.c | ||
| sp_tint.c | ||
| sp_tlong.c | ||