forked from Minki/linux
7727eaa449
v3.3 introduced 16 sources PQ operations. This also introduced super extended descriptors to support the 16 srcs operations. This patch adds support for the 16 sources ops and in turn adds the super extended descriptors for those ops. 5 SED pools are created depending on the descriptor sizes. An SED can be a 64 bytes sized descriptor or larger and must be physically contiguous. A kmem cache pool is created for allocating the software descriptor that manages the hardware descriptor. The super extended descriptor will take place of extended descriptor under certain operations and be "attached" to the op descriptor during operation. This is a new feature for ioatdma v3.3. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Acked-by: Dan Williams <djbw@fb.com> Acked-by: Dan Williams <djbw@fb.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
182 lines
5.9 KiB
C
182 lines
5.9 KiB
C
/*
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* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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#ifndef IOATDMA_V2_H
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#define IOATDMA_V2_H
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#include <linux/dmaengine.h>
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#include <linux/circ_buf.h>
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#include "dma.h"
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#include "hw.h"
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extern int ioat_pending_level;
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extern int ioat_ring_alloc_order;
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/*
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* workaround for IOAT ver.3.0 null descriptor issue
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* (channel returns error when size is 0)
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*/
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#define NULL_DESC_BUFFER_SIZE 1
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#define IOAT_MAX_ORDER 16
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#define ioat_get_alloc_order() \
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(min(ioat_ring_alloc_order, IOAT_MAX_ORDER))
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#define ioat_get_max_alloc_order() \
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(min(ioat_ring_max_alloc_order, IOAT_MAX_ORDER))
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/* struct ioat2_dma_chan - ioat v2 / v3 channel attributes
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* @base: common ioat channel parameters
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* @xfercap_log; log2 of channel max transfer length (for fast division)
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* @head: allocated index
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* @issued: hardware notification point
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* @tail: cleanup index
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* @dmacount: identical to 'head' except for occasionally resetting to zero
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* @alloc_order: log2 of the number of allocated descriptors
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* @produce: number of descriptors to produce at submit time
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* @ring: software ring buffer implementation of hardware ring
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* @prep_lock: serializes descriptor preparation (producers)
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*/
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struct ioat2_dma_chan {
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struct ioat_chan_common base;
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size_t xfercap_log;
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u16 head;
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u16 issued;
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u16 tail;
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u16 dmacount;
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u16 alloc_order;
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u16 produce;
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struct ioat_ring_ent **ring;
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spinlock_t prep_lock;
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};
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static inline struct ioat2_dma_chan *to_ioat2_chan(struct dma_chan *c)
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{
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struct ioat_chan_common *chan = to_chan_common(c);
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return container_of(chan, struct ioat2_dma_chan, base);
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}
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static inline u32 ioat2_ring_size(struct ioat2_dma_chan *ioat)
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{
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return 1 << ioat->alloc_order;
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}
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/* count of descriptors in flight with the engine */
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static inline u16 ioat2_ring_active(struct ioat2_dma_chan *ioat)
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{
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return CIRC_CNT(ioat->head, ioat->tail, ioat2_ring_size(ioat));
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}
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/* count of descriptors pending submission to hardware */
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static inline u16 ioat2_ring_pending(struct ioat2_dma_chan *ioat)
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{
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return CIRC_CNT(ioat->head, ioat->issued, ioat2_ring_size(ioat));
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}
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static inline u32 ioat2_ring_space(struct ioat2_dma_chan *ioat)
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{
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return ioat2_ring_size(ioat) - ioat2_ring_active(ioat);
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}
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static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len)
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{
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u16 num_descs = len >> ioat->xfercap_log;
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num_descs += !!(len & ((1 << ioat->xfercap_log) - 1));
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return num_descs;
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}
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/**
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* struct ioat_ring_ent - wrapper around hardware descriptor
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* @hw: hardware DMA descriptor (for memcpy)
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* @fill: hardware fill descriptor
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* @xor: hardware xor descriptor
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* @xor_ex: hardware xor extension descriptor
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* @pq: hardware pq descriptor
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* @pq_ex: hardware pq extension descriptor
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* @pqu: hardware pq update descriptor
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* @raw: hardware raw (un-typed) descriptor
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* @txd: the generic software descriptor for all engines
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* @len: total transaction length for unmap
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* @result: asynchronous result of validate operations
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* @id: identifier for debug
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*/
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struct ioat_ring_ent {
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union {
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struct ioat_dma_descriptor *hw;
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struct ioat_fill_descriptor *fill;
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struct ioat_xor_descriptor *xor;
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struct ioat_xor_ext_descriptor *xor_ex;
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struct ioat_pq_descriptor *pq;
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struct ioat_pq_ext_descriptor *pq_ex;
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struct ioat_pq_update_descriptor *pqu;
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struct ioat_raw_descriptor *raw;
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};
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size_t len;
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struct dma_async_tx_descriptor txd;
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enum sum_check_flags *result;
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#ifdef DEBUG
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int id;
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#endif
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struct ioat_sed_ent *sed;
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};
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static inline struct ioat_ring_ent *
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ioat2_get_ring_ent(struct ioat2_dma_chan *ioat, u16 idx)
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{
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return ioat->ring[idx & (ioat2_ring_size(ioat) - 1)];
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}
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static inline void ioat2_set_chainaddr(struct ioat2_dma_chan *ioat, u64 addr)
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{
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struct ioat_chan_common *chan = &ioat->base;
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writel(addr & 0x00000000FFFFFFFF,
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chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
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writel(addr >> 32,
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chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
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}
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int ioat2_dma_probe(struct ioatdma_device *dev, int dca);
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int ioat3_dma_probe(struct ioatdma_device *dev, int dca);
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void ioat3_dma_remove(struct ioatdma_device *dev);
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struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
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struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase);
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int ioat2_check_space_lock(struct ioat2_dma_chan *ioat, int num_descs);
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int ioat2_enumerate_channels(struct ioatdma_device *device);
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struct dma_async_tx_descriptor *
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ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
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dma_addr_t dma_src, size_t len, unsigned long flags);
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void ioat2_issue_pending(struct dma_chan *chan);
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int ioat2_alloc_chan_resources(struct dma_chan *c);
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void ioat2_free_chan_resources(struct dma_chan *c);
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void __ioat2_restart_chan(struct ioat2_dma_chan *ioat);
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bool reshape_ring(struct ioat2_dma_chan *ioat, int order);
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void __ioat2_issue_pending(struct ioat2_dma_chan *ioat);
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void ioat2_cleanup_event(unsigned long data);
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void ioat2_timer_event(unsigned long data);
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int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo);
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int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo);
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extern struct kobj_type ioat2_ktype;
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extern struct kmem_cache *ioat2_cache;
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#endif /* IOATDMA_V2_H */
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