forked from Minki/linux
7710cc691c
Currently, with MPU enabled, we prohibit userspace access to anything except RAM. Benjamin, reported that because of that his userspace application cannot access framebuffer's memory he reserved in device tree. It turns out we have no option other than to allow userspace access memory covered by background region. Reported-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Tested-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
485 lines
11 KiB
C
485 lines
11 KiB
C
/*
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* Based on linux/arch/arm/mm/nommu.c
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*
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* ARM PMSAv7 supporting functions.
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*/
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#include <linux/bitops.h>
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#include <linux/memblock.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/cputype.h>
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#include <asm/mpu.h>
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#include <asm/sections.h>
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#include "mm.h"
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struct region {
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phys_addr_t base;
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phys_addr_t size;
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unsigned long subreg;
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};
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static struct region __initdata mem[MPU_MAX_REGIONS];
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#ifdef CONFIG_XIP_KERNEL
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static struct region __initdata xip[MPU_MAX_REGIONS];
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#endif
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static unsigned int __initdata mpu_min_region_order;
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static unsigned int __initdata mpu_max_regions;
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static int __init __mpu_min_region_order(void);
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static int __init __mpu_max_regions(void);
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#ifndef CONFIG_CPU_V7M
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#define DRBAR __ACCESS_CP15(c6, 0, c1, 0)
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#define IRBAR __ACCESS_CP15(c6, 0, c1, 1)
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#define DRSR __ACCESS_CP15(c6, 0, c1, 2)
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#define IRSR __ACCESS_CP15(c6, 0, c1, 3)
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#define DRACR __ACCESS_CP15(c6, 0, c1, 4)
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#define IRACR __ACCESS_CP15(c6, 0, c1, 5)
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#define RNGNR __ACCESS_CP15(c6, 0, c2, 0)
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/* Region number */
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static inline void rgnr_write(u32 v)
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{
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write_sysreg(v, RNGNR);
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}
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/* Data-side / unified region attributes */
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/* Region access control register */
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static inline void dracr_write(u32 v)
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{
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write_sysreg(v, DRACR);
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}
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/* Region size register */
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static inline void drsr_write(u32 v)
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{
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write_sysreg(v, DRSR);
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}
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/* Region base address register */
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static inline void drbar_write(u32 v)
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{
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write_sysreg(v, DRBAR);
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}
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static inline u32 drbar_read(void)
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{
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return read_sysreg(DRBAR);
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}
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/* Optional instruction-side region attributes */
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/* I-side Region access control register */
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static inline void iracr_write(u32 v)
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{
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write_sysreg(v, IRACR);
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}
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/* I-side Region size register */
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static inline void irsr_write(u32 v)
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{
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write_sysreg(v, IRSR);
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}
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/* I-side Region base address register */
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static inline void irbar_write(u32 v)
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{
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write_sysreg(v, IRBAR);
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}
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static inline u32 irbar_read(void)
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{
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return read_sysreg(IRBAR);
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}
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#else
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static inline void rgnr_write(u32 v)
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{
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writel_relaxed(v, BASEADDR_V7M_SCB + MPU_RNR);
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}
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/* Data-side / unified region attributes */
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/* Region access control register */
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static inline void dracr_write(u32 v)
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{
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u32 rsr = readl_relaxed(BASEADDR_V7M_SCB + MPU_RASR) & GENMASK(15, 0);
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writel_relaxed((v << 16) | rsr, BASEADDR_V7M_SCB + MPU_RASR);
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}
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/* Region size register */
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static inline void drsr_write(u32 v)
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{
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u32 racr = readl_relaxed(BASEADDR_V7M_SCB + MPU_RASR) & GENMASK(31, 16);
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writel_relaxed(v | racr, BASEADDR_V7M_SCB + MPU_RASR);
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}
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/* Region base address register */
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static inline void drbar_write(u32 v)
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{
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writel_relaxed(v, BASEADDR_V7M_SCB + MPU_RBAR);
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}
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static inline u32 drbar_read(void)
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{
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return readl_relaxed(BASEADDR_V7M_SCB + MPU_RBAR);
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}
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/* ARMv7-M only supports a unified MPU, so I-side operations are nop */
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static inline void iracr_write(u32 v) {}
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static inline void irsr_write(u32 v) {}
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static inline void irbar_write(u32 v) {}
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static inline unsigned long irbar_read(void) {return 0;}
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#endif
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static int __init mpu_present(void)
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{
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return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
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}
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static bool __init try_split_region(phys_addr_t base, phys_addr_t size, struct region *region)
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{
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unsigned long subreg, bslots, sslots;
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phys_addr_t abase = base & ~(size - 1);
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phys_addr_t asize = base + size - abase;
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phys_addr_t p2size = 1 << __fls(asize);
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phys_addr_t bdiff, sdiff;
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if (p2size != asize)
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p2size *= 2;
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bdiff = base - abase;
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sdiff = p2size - asize;
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subreg = p2size / MPU_NR_SUBREGS;
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if ((bdiff % subreg) || (sdiff % subreg))
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return false;
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bslots = bdiff / subreg;
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sslots = sdiff / subreg;
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if (bslots || sslots) {
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int i;
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if (subreg < MPU_MIN_SUBREG_SIZE)
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return false;
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if (bslots + sslots > MPU_NR_SUBREGS)
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return false;
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for (i = 0; i < bslots; i++)
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_set_bit(i, ®ion->subreg);
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for (i = 1; i <= sslots; i++)
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_set_bit(MPU_NR_SUBREGS - i, ®ion->subreg);
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}
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region->base = abase;
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region->size = p2size;
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return true;
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}
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static int __init allocate_region(phys_addr_t base, phys_addr_t size,
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unsigned int limit, struct region *regions)
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{
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int count = 0;
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phys_addr_t diff = size;
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int attempts = MPU_MAX_REGIONS;
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while (diff) {
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/* Try cover region as is (maybe with help of subregions) */
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if (try_split_region(base, size, ®ions[count])) {
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count++;
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base += size;
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diff -= size;
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size = diff;
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} else {
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/*
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* Maximum aligned region might overflow phys_addr_t
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* if "base" is 0. Hence we keep everything below 4G
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* until we take the smaller of the aligned region
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* size ("asize") and rounded region size ("p2size"),
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* one of which is guaranteed to be smaller than the
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* maximum physical address.
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*/
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phys_addr_t asize = (base - 1) ^ base;
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phys_addr_t p2size = (1 << __fls(diff)) - 1;
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size = asize < p2size ? asize + 1 : p2size + 1;
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}
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if (count > limit)
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break;
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if (!attempts)
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break;
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attempts--;
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}
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return count;
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}
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/* MPU initialisation functions */
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void __init adjust_lowmem_bounds_mpu(void)
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{
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phys_addr_t specified_mem_size = 0, total_mem_size = 0;
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struct memblock_region *reg;
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bool first = true;
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phys_addr_t mem_start;
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phys_addr_t mem_end;
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unsigned int mem_max_regions;
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int num, i;
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if (!mpu_present())
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return;
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/* Free-up MPU_PROBE_REGION */
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mpu_min_region_order = __mpu_min_region_order();
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/* How many regions are supported */
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mpu_max_regions = __mpu_max_regions();
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mem_max_regions = min((unsigned int)MPU_MAX_REGIONS, mpu_max_regions);
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/* We need to keep one slot for background region */
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mem_max_regions--;
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#ifndef CONFIG_CPU_V7M
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/* ... and one for vectors */
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mem_max_regions--;
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#endif
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#ifdef CONFIG_XIP_KERNEL
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/* plus some regions to cover XIP ROM */
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num = allocate_region(CONFIG_XIP_PHYS_ADDR, __pa(_exiprom) - CONFIG_XIP_PHYS_ADDR,
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mem_max_regions, xip);
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mem_max_regions -= num;
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#endif
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for_each_memblock(memory, reg) {
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if (first) {
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phys_addr_t phys_offset = PHYS_OFFSET;
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/*
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* Initially only use memory continuous from
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* PHYS_OFFSET */
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if (reg->base != phys_offset)
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panic("First memory bank must be contiguous from PHYS_OFFSET");
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mem_start = reg->base;
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mem_end = reg->base + reg->size;
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specified_mem_size = reg->size;
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first = false;
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} else {
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/*
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* memblock auto merges contiguous blocks, remove
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* all blocks afterwards in one go (we can't remove
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* blocks separately while iterating)
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*/
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pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
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&mem_end, ®->base);
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memblock_remove(reg->base, 0 - reg->base);
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break;
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}
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}
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num = allocate_region(mem_start, specified_mem_size, mem_max_regions, mem);
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for (i = 0; i < num; i++) {
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unsigned long subreg = mem[i].size / MPU_NR_SUBREGS;
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total_mem_size += mem[i].size - subreg * hweight_long(mem[i].subreg);
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pr_debug("MPU: base %pa size %pa disable subregions: %*pbl\n",
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&mem[i].base, &mem[i].size, MPU_NR_SUBREGS, &mem[i].subreg);
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}
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if (total_mem_size != specified_mem_size) {
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pr_warn("Truncating memory from %pa to %pa (MPU region constraints)",
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&specified_mem_size, &total_mem_size);
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memblock_remove(mem_start + total_mem_size,
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specified_mem_size - total_mem_size);
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}
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}
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static int __init __mpu_max_regions(void)
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{
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/*
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* We don't support a different number of I/D side regions so if we
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* have separate instruction and data memory maps then return
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* whichever side has a smaller number of supported regions.
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*/
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u32 dregions, iregions, mpuir;
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mpuir = read_cpuid_mputype();
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dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
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/* Check for separate d-side and i-side memory maps */
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if (mpuir & MPUIR_nU)
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iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
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/* Use the smallest of the two maxima */
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return min(dregions, iregions);
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}
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static int __init mpu_iside_independent(void)
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{
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/* MPUIR.nU specifies whether there is *not* a unified memory map */
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return read_cpuid_mputype() & MPUIR_nU;
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}
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static int __init __mpu_min_region_order(void)
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{
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u32 drbar_result, irbar_result;
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/* We've kept a region free for this probing */
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rgnr_write(MPU_PROBE_REGION);
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isb();
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/*
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* As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
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* region order
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*/
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drbar_write(0xFFFFFFFC);
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drbar_result = irbar_result = drbar_read();
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drbar_write(0x0);
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/* If the MPU is non-unified, we use the larger of the two minima*/
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if (mpu_iside_independent()) {
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irbar_write(0xFFFFFFFC);
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irbar_result = irbar_read();
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irbar_write(0x0);
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}
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isb(); /* Ensure that MPU region operations have completed */
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/* Return whichever result is larger */
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return __ffs(max(drbar_result, irbar_result));
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}
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static int __init mpu_setup_region(unsigned int number, phys_addr_t start,
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unsigned int size_order, unsigned int properties,
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unsigned int subregions, bool need_flush)
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{
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u32 size_data;
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/* We kept a region free for probing resolution of MPU regions*/
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if (number > mpu_max_regions
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|| number >= MPU_MAX_REGIONS)
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return -ENOENT;
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if (size_order > 32)
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return -ENOMEM;
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if (size_order < mpu_min_region_order)
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return -ENOMEM;
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/* Writing N to bits 5:1 (RSR_SZ) specifies region size 2^N+1 */
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size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN;
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size_data |= subregions << MPU_RSR_SD;
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if (need_flush)
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flush_cache_all();
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dsb(); /* Ensure all previous data accesses occur with old mappings */
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rgnr_write(number);
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isb();
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drbar_write(start);
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dracr_write(properties);
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isb(); /* Propagate properties before enabling region */
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drsr_write(size_data);
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/* Check for independent I-side registers */
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if (mpu_iside_independent()) {
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irbar_write(start);
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iracr_write(properties);
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isb();
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irsr_write(size_data);
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}
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isb();
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/* Store region info (we treat i/d side the same, so only store d) */
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mpu_rgn_info.rgns[number].dracr = properties;
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mpu_rgn_info.rgns[number].drbar = start;
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mpu_rgn_info.rgns[number].drsr = size_data;
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mpu_rgn_info.used++;
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return 0;
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}
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/*
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* Set up default MPU regions, doing nothing if there is no MPU
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*/
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void __init mpu_setup(void)
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{
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int i, region = 0, err = 0;
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if (!mpu_present())
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return;
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/* Setup MPU (order is important) */
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/* Background */
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err |= mpu_setup_region(region++, 0, 32,
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MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0RW,
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0, false);
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#ifdef CONFIG_XIP_KERNEL
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/* ROM */
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for (i = 0; i < ARRAY_SIZE(xip); i++) {
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/*
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* In case we overwrite RAM region we set earlier in
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* head-nommu.S (which is cachable) all subsequent
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* data access till we setup RAM bellow would be done
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* with BG region (which is uncachable), thus we need
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* to clean and invalidate cache.
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*/
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bool need_flush = region == MPU_RAM_REGION;
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if (!xip[i].size)
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continue;
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err |= mpu_setup_region(region++, xip[i].base, ilog2(xip[i].size),
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MPU_AP_PL1RO_PL0NA | MPU_RGN_NORMAL,
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xip[i].subreg, need_flush);
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}
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#endif
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/* RAM */
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for (i = 0; i < ARRAY_SIZE(mem); i++) {
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if (!mem[i].size)
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continue;
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err |= mpu_setup_region(region++, mem[i].base, ilog2(mem[i].size),
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MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL,
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mem[i].subreg, false);
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}
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/* Vectors */
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#ifndef CONFIG_CPU_V7M
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err |= mpu_setup_region(region++, vectors_base, ilog2(2 * PAGE_SIZE),
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MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL,
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0, false);
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#endif
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if (err) {
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panic("MPU region initialization failure! %d", err);
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} else {
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pr_info("Using ARMv7 PMSA Compliant MPU. "
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"Region independence: %s, Used %d of %d regions\n",
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mpu_iside_independent() ? "Yes" : "No",
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mpu_rgn_info.used, mpu_max_regions);
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}
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}
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