linux/drivers/gpu
Chris Wilson 7707225856 drm/i915: HSW always use GGTT selector for secure batches
gen6 and earlier conflate address space selection (ppgtt vs ggtt) with
the security bit (i.e. only privileged batches were allowed to run from
ggtt). From Haswell only, you are able to select the security bit
separate from the address space - and we always requested to use ppgtt.
This breaks the golden render state batch execution with full-ppgtt as
that is only present in the global GTT and more generally any secure
batch that is not colocated in the ppgtt and ggtt. So we need to
disable the use of the ppgtt selector bit for secure batches, or else we
hang immediately upon boot and thence after every GPU reset...

v2: Only HSW differentiates between secure dispatch and ggtt, so simply
ignore the differentiation and always use secure==ggtt.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Rectify commit message as noted by Chris.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-19 14:41:18 +02:00
..
drm drm/i915: HSW always use GGTT selector for secure batches 2014-09-19 14:41:18 +02:00
host1x drm/tegra: Make job submission 64-bit safe 2014-08-04 10:07:36 +02:00
ipu-v3 gpu: ipu-v3: Add ipu_dump() 2014-09-02 14:55:56 +02:00
vga vgaarb: We can own non-decoded resources 2014-07-08 11:15:09 +10:00
Makefile gpu: ipu-v3: Move i.MX IPUv3 core driver out of staging 2014-06-04 11:06:52 +02:00