Andrew Jeffery 8ccb6dc6e9 pinctrl: aspeed: g4: Fix mux configuration for GPIOs AA[4-7], AB[0-7] ... Incorrect video output configuration bits were being tested on pins in GPIO banks AA and AB for the ROM{8,16} mux functions. The ROM{8,16} functions are the highest priority for the relevant pins and also the default function, so we require the relevant video output configuration be disabled to mux GPIO functionality. As the wrong bits were being tested a GPIO export would succeed but leave the pin in an unresponsive state (i.e. value updates were ignored). This misbehaviour was discovered as part of extending the GPIO controller's support to cover banks Y, Z, AA, AB and AC (AC in the case of the g5 SoC). Fixes: 6d329f14a7 ("pinctrl: aspeed-g4: Add mux configuration for all pins") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>		2017-01-26 14:42:39 +01:00
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Kconfig	pinctrl: Add pinctrl-aspeed-g5 driver	2016-09-07 16:53:37 +02:00
Makefile	pinctrl: Add pinctrl-aspeed-g5 driver	2016-09-07 16:53:37 +02:00
pinctrl-aspeed-g4.c	pinctrl: aspeed: g4: Fix mux configuration for GPIOs AA[4-7], AB[0-7]	2017-01-26 14:42:39 +01:00
pinctrl-aspeed-g5.c	pinctrl: aspeed-g5: Add mux configuration for all pins	2016-12-28 01:21:23 +01:00
pinctrl-aspeed.c	pinctrl: aspeed: Fix kerneldoc return descriptions	2016-12-28 01:23:10 +01:00
pinctrl-aspeed.h	pinctrl: aspeed-g5: Add mux configuration for all pins	2016-12-28 01:21:23 +01:00