forked from Minki/linux
76c23c32e3
Fix ECC Correction bug where the byte offset location were double
fliped causing correction routine to toggle the wrong byte location
in the ECC segment. The ndfc_calculate_ecc routine change the order
of getting the ECC code.
/* The NDFC uses Smart Media (SMC) bytes order */
ecc_code[0] = p[2];
ecc_code[1] = p[1];
ecc_code[2] = p[3];
But in the Correction algorithm when calculating the byte offset
location, the b1 is used as the upper part of the address. Which
again reverse the order making the final byte offset address
location incorrect.
byte_addr = (addressbits[b1] << 4) + addressbits[b0];
The order is change to read it in straight and let the correction
function to revert it to SMC order.
Cc: stable@kernel.org
Signed-off-by: Feng Kan <fkan@amcc.com>
Acked-by: Victor Gallardo <vgallardo@amcc.com>
Acked-by: Prodyut Hazarika <phazarika@amcc.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
319 lines
7.4 KiB
C
319 lines
7.4 KiB
C
/*
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* drivers/mtd/ndfc.c
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*
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* Overview:
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* Platform independent driver for NDFC (NanD Flash Controller)
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* integrated into EP440 cores
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*
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* Ported to an OF platform driver by Sean MacLennan
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*
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* The NDFC supports multiple chips, but this driver only supports a
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* single chip since I do not have access to any boards with
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* multiple chips.
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*
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* Author: Thomas Gleixner
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*
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* Copyright 2006 IBM
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* Copyright 2008 PIKA Technologies
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* Sean MacLennan <smaclennan@pikatech.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/ndfc.h>
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#include <linux/mtd/mtd.h>
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#include <linux/of_platform.h>
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#include <asm/io.h>
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struct ndfc_controller {
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struct of_device *ofdev;
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void __iomem *ndfcbase;
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struct mtd_info mtd;
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struct nand_chip chip;
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int chip_select;
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struct nand_hw_control ndfc_control;
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#ifdef CONFIG_MTD_PARTITIONS
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struct mtd_partition *parts;
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#endif
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};
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static struct ndfc_controller ndfc_ctrl;
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static void ndfc_select_chip(struct mtd_info *mtd, int chip)
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{
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uint32_t ccr;
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
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if (chip >= 0) {
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ccr &= ~NDFC_CCR_BS_MASK;
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ccr |= NDFC_CCR_BS(chip + ndfc->chip_select);
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} else
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ccr |= NDFC_CCR_RESET_CE;
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out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
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}
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static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD);
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else
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writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE);
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}
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static int ndfc_ready(struct mtd_info *mtd)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
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}
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static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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uint32_t ccr;
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
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ccr |= NDFC_CCR_RESET_ECC;
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out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
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wmb();
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}
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static int ndfc_calculate_ecc(struct mtd_info *mtd,
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const u_char *dat, u_char *ecc_code)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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uint32_t ecc;
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uint8_t *p = (uint8_t *)&ecc;
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wmb();
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ecc = in_be32(ndfc->ndfcbase + NDFC_ECC);
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/* The NDFC uses Smart Media (SMC) bytes order */
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ecc_code[0] = p[1];
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ecc_code[1] = p[2];
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ecc_code[2] = p[3];
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return 0;
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}
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/*
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* Speedups for buffer read/write/verify
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*
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* NDFC allows 32bit read/write of data. So we can speed up the buffer
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* functions. No further checking, as nand_base will always read/write
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* page aligned.
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*/
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static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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uint32_t *p = (uint32_t *) buf;
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for(;len > 0; len -= 4)
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*p++ = in_be32(ndfc->ndfcbase + NDFC_DATA);
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}
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static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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uint32_t *p = (uint32_t *) buf;
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for(;len > 0; len -= 4)
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out_be32(ndfc->ndfcbase + NDFC_DATA, *p++);
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}
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static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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uint32_t *p = (uint32_t *) buf;
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for(;len > 0; len -= 4)
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if (*p++ != in_be32(ndfc->ndfcbase + NDFC_DATA))
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return -EFAULT;
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return 0;
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}
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/*
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* Initialize chip structure
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*/
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static int ndfc_chip_init(struct ndfc_controller *ndfc,
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struct device_node *node)
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{
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#ifdef CONFIG_MTD_PARTITIONS
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#ifdef CONFIG_MTD_CMDLINE_PARTS
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static const char *part_types[] = { "cmdlinepart", NULL };
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#else
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static const char *part_types[] = { NULL };
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#endif
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#endif
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struct device_node *flash_np;
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struct nand_chip *chip = &ndfc->chip;
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int ret;
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chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
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chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
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chip->cmd_ctrl = ndfc_hwcontrol;
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chip->dev_ready = ndfc_ready;
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chip->select_chip = ndfc_select_chip;
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chip->chip_delay = 50;
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chip->controller = &ndfc->ndfc_control;
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chip->read_buf = ndfc_read_buf;
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chip->write_buf = ndfc_write_buf;
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chip->verify_buf = ndfc_verify_buf;
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chip->ecc.correct = nand_correct_data;
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chip->ecc.hwctl = ndfc_enable_hwecc;
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chip->ecc.calculate = ndfc_calculate_ecc;
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.size = 256;
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chip->ecc.bytes = 3;
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ndfc->mtd.priv = chip;
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ndfc->mtd.owner = THIS_MODULE;
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flash_np = of_get_next_child(node, NULL);
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if (!flash_np)
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return -ENODEV;
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ndfc->mtd.name = kasprintf(GFP_KERNEL, "%s.%s",
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dev_name(&ndfc->ofdev->dev), flash_np->name);
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if (!ndfc->mtd.name) {
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ret = -ENOMEM;
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goto err;
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}
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ret = nand_scan(&ndfc->mtd, 1);
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if (ret)
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goto err;
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#ifdef CONFIG_MTD_PARTITIONS
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ret = parse_mtd_partitions(&ndfc->mtd, part_types, &ndfc->parts, 0);
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if (ret < 0)
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goto err;
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#ifdef CONFIG_MTD_OF_PARTS
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if (ret == 0) {
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ret = of_mtd_parse_partitions(&ndfc->ofdev->dev, flash_np,
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&ndfc->parts);
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if (ret < 0)
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goto err;
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}
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#endif
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if (ret > 0)
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ret = add_mtd_partitions(&ndfc->mtd, ndfc->parts, ret);
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else
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#endif
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ret = add_mtd_device(&ndfc->mtd);
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err:
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of_node_put(flash_np);
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if (ret)
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kfree(ndfc->mtd.name);
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return ret;
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}
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static int __devinit ndfc_probe(struct of_device *ofdev,
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const struct of_device_id *match)
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{
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struct ndfc_controller *ndfc = &ndfc_ctrl;
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const u32 *reg;
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u32 ccr;
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int err, len;
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spin_lock_init(&ndfc->ndfc_control.lock);
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init_waitqueue_head(&ndfc->ndfc_control.wq);
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ndfc->ofdev = ofdev;
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dev_set_drvdata(&ofdev->dev, ndfc);
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/* Read the reg property to get the chip select */
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reg = of_get_property(ofdev->node, "reg", &len);
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if (reg == NULL || len != 12) {
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dev_err(&ofdev->dev, "unable read reg property (%d)\n", len);
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return -ENOENT;
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}
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ndfc->chip_select = reg[0];
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ndfc->ndfcbase = of_iomap(ofdev->node, 0);
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if (!ndfc->ndfcbase) {
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dev_err(&ofdev->dev, "failed to get memory\n");
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return -EIO;
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}
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ccr = NDFC_CCR_BS(ndfc->chip_select);
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/* It is ok if ccr does not exist - just default to 0 */
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reg = of_get_property(ofdev->node, "ccr", NULL);
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if (reg)
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ccr |= *reg;
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out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
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/* Set the bank settings if given */
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reg = of_get_property(ofdev->node, "bank-settings", NULL);
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if (reg) {
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int offset = NDFC_BCFG0 + (ndfc->chip_select << 2);
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out_be32(ndfc->ndfcbase + offset, *reg);
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}
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err = ndfc_chip_init(ndfc, ofdev->node);
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if (err) {
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iounmap(ndfc->ndfcbase);
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return err;
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}
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return 0;
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}
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static int __devexit ndfc_remove(struct of_device *ofdev)
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{
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struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev);
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nand_release(&ndfc->mtd);
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return 0;
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}
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static const struct of_device_id ndfc_match[] = {
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{ .compatible = "ibm,ndfc", },
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{}
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};
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MODULE_DEVICE_TABLE(of, ndfc_match);
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static struct of_platform_driver ndfc_driver = {
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.driver = {
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.name = "ndfc",
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},
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.match_table = ndfc_match,
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.probe = ndfc_probe,
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.remove = __devexit_p(ndfc_remove),
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};
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static int __init ndfc_nand_init(void)
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{
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return of_register_platform_driver(&ndfc_driver);
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}
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static void __exit ndfc_nand_exit(void)
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{
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of_unregister_platform_driver(&ndfc_driver);
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}
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module_init(ndfc_nand_init);
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module_exit(ndfc_nand_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
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MODULE_DESCRIPTION("OF Platform driver for NDFC");
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